Abstract: A voltage recovery circuit in an integrated circuit is provided. The voltage recovery circuit includes a bootstrap circuit coupled to a cascode switch circuit. The bootstrap circuit includes a first transistor coupled in series to a second transistor, a resistive element is coupled between the second transistor and an output of the voltage recovery circuit, and a capacitive element is coupled between control electrodes of the first and second transistors and the output. The cascode switch circuit includes a third and fourth transistor coupled in series. The third transistor includes a current electrode coupled to receive a first input voltage, and a control electrode coupled to the control electrodes of the first and second transistors. The fourth transistor includes a current electrode coupled to the output, and a control electrode coupled to a current electrode of the second transistor and a terminal of the resistive element.

Abstract: A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.

Abstract: A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharging a selected bitline to a first predetermined voltage in response to a first precharge signal. The current-to-voltage converter has a current input coupled to the selected bitline, and a voltage output. A latch circuit has a storage node coupled to the voltage output of the current-to-voltage converter. The second precharge circuit is for precharging the storage node of the latch circuit to a second predetermined voltage in response to a second precharge signal.

Abstract: A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.

Abstract: A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.

Abstract: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes, for example, a plurality of parallel-connected transistors (112) coupled between the array (12) of non-volatile memory cells and a power supply terminal.

Abstract: An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes a reference current generator (34) for providing a reference current. A first current mirror (46) is coupled to the reference current generator (34) and provides a first predetermined discharge current for discharging the control gate, drain, and source. A second current mirror (36) is coupled to the reference current generator (34) and provides a second predetermined discharge current for discharging the well terminals after the erase operation.

Abstract: An apparatus and method for detecting the presence or absence of a container cover and for determining how much food is present in a microwave oven. The apparatus includes a sensor for sensing the state of an exhaust from the heating chamber in the microwave oven, and a sensor output processor for processing a signal from the sensor, calculating cooking information according to the signal, and identifying the presence or absence of a container cover and determining how much food is present by utilizing the cooking information and inputted cooking time information to provide a control signal for controlling a heating time of said heating chamber.