Patents by Inventor Jon D. Garlett

Jon D. Garlett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7085970
    Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gareth J. Nicholls, Alexander H. Ainscow, Jon D. Garlett, Bobak Modaress-Razavi, Vernon R. Norman, Martin L. Schmatz
  • Patent number: 7038319
    Abstract: A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Charles S. Chiu, Jon D. Garlett, Louis L. Hsu, Brian J. Schuh
  • Publication number: 20040019837
    Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.
    Type: Application
    Filed: July 23, 2002
    Publication date: January 29, 2004
    Applicant: International Business Machines Corporation
    Inventors: Gareth J. Nicholls, Alexander H. Ainscow, Jon D. Garlett, Bobak Modaress-Razavi, Vernon R. Norman, Martin L. Schmatz