Abstract: A processor may determine, for each subdevice of a set of subdevices of a storage enclosure device, one or more reliability measures of the subdevice. A processor may determine, based at least on the one or more reliability measures for the subdevices and a spatial layout rule, a set of striping groups that maximizes a reliability of the set of subdevices of the storage enclosure device, each of the striping groups including a respective subset of the set of subdevices, wherein the spatial layout rule prescribes a geometric layout of the subdevices within striping groups across the storage enclosure device. A processor may store output data of a data striping operation to a particular subset of subdevices associated with a particular striping group of the set of striping groups.

Abstract: Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Abstract: Described are hard disk drives (HDDs) operable for archival applications and utilizing the same mechanical and electrical design of conventional HDDs. The capacity of a conventional HDD may be extended by up to 25% to 40% or more by employing multiple write and/or read spins before declaring success in write and read processes. The multiple write and/or read spins are designed to address the lower reliability that would otherwise result from high density packing of the data, at the cost of reducing performance. The result is an HDD with lower performance at higher capacity without sacrificing reliability and without altering conventional HDD mechanical or electrical design.

Abstract: Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Abstract: A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Abstract: A data storage system for use in a high radiation environment has a radiation-hardened storage controller that measures a current draw of a storage drive in a storage array. The storage drive is not radiation-hardened. Based on a characteristic of the current draw, a latch up is detected the storage drive. Based on the detected latch up, power is removed from all or part of the storage drive. After a cooling period has elapsed, the power is reapplied to the storage drive.

Abstract: A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation.

Abstract: A data storage system for use in a high radiation environment runs first and second operating time counters to monitor a field-programmable, gate array (FPGA) configured as a storage controller. Based on the first operating time counter passing a first threshold, the FPGA is fully reprogrammed. Based on the second operating time counter passing a second threshold less than the first threshold, the FPGA is partially reprogrammed.

Abstract: A failure of a head is detected, the head reading from and writing to an affected surface of a disk of a disk drive. The failure prevents the head from writing to the affected surface but does not prevent the head from reading from the affected surface. In response to detecting the failure, a remediation is performed. The remediation involves determining spare capacity blocks on other surfaces of the disk drive different than the affected surface, and copying data from the affected surface to the spare capacity blocks via an internal copy function within the disk drive. The spare capacity blocks in place of the affected surface for data storage and retrieval subsequent to the failure.

Abstract: A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

Abstract: A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Abstract: The technology disclosed herein provides a memory blade including a plurality of fabric switches configured to receive commands from a plurality of host clients, an address decoder and tracker circuit communicatively connected to the fabric switches and configured to determine the source of commands received at the fabric switches an aggregator crossbar configured to provide bandwidth aggregation between host clients and a plurality of memory modules; and a buffer module configured to couple the commands from the plurality of host clients with the plurality of memory modules.

Abstract: A data storage system for use in a high radiation environment runs first and second operating time counters to monitor a field-programmable, gate array (FPGA) configured as a storage controller. Based on the first operating time counter passing a first threshold, the FPGA is fully reprogrammed. Based on the second operating time counter passing a second threshold less than the first threshold, the FPGA is partially reprogrammed.

Abstract: A data storage chassis includes a plurality of data storage cartridges, and printed circuit board assembly (PCBA) electronics selectively connectable to one or more of the plurality of data storage cartridges. The data storage chassis also includes a wireless interface controller communicatively coupled to the PCBA electronics. The wireless interface controller facilitates wireless communication of data between the data storage chassis and a host using at least one frequency in a range of frequencies including fifth-generation (5G), millimeter, and sub-millimeter frequency ranges.

Abstract: A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Abstract: A data storage system for use in a high radiation environment includes an array of storage drives. Each storage drive includes a non-radiation-hardened drive controller, a non-radiation-hardened, non-volatile, storage medium, and a non-radiation-hardened volatile memory. The system includes a radiation-hardened storage controller coupled to the array. The radiation-hardened storage controller provides failure-resistant data redundancy among the storage drives of the array and provides host access to the array.

Abstract: A data storage apparatus is presented that includes a well structure comprising a suspension medium, and a magnetic particle disposed in at least a portion of the well structure. A control system is configured to represent a data state corresponding to a positioning of the magnetic particle within the well structure, the magnetic particle moved responsive to an applied field and a present material state of the well structure. Various addressable arrays of well structures and associated control elements can be established to form data storage devices.

Abstract: Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

Abstract: Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Abstract: A system for use in an aerospace environment includes an array of storage drives each comprising a non-radiation-hardened drive controller, a non-radiation-hardened, non-volatile, storage medium, and a non-radiation-hardened volatile memory. The system includes a radiation-tolerant storage controller coupled to the array. The storage controller provides failure-resistant data redundancy among the storage drives of the array. The system includes a bus host that accesses the array via the storage controller. The storage controller implements security logic and a root-of-trust that provides to the bus host verification of authenticity of the radiation tolerant storage controller and the storage drives.