Abstract: A method for designing a scan path to connect flip-flops in a logic circuit. Test patterns are created by the circuit designer. The circuit and test patterns are then simulated to determine potential faults in the circuit which are not detected by the patterns and not observable at any flip-flop in the circuit. The number of such faults is then reduced. For example, the test patterns can be modified and/or redundant circuit elements can be removed. A subset of flip-flops where undetectable faults are observable are then identified and connected in a scan path. Scan times can also be selected. The method may be extended to include the actual testing of the logic circuit.