Abstract: An inductor device includes a first inductor, a switch, and a second inductor. The first inductor includes a first, a second, a third, and a fourth trace. The first trace is disposed at a first area of the inductor device. The second trace is disposed inside the first trace. The third trace is disposed at a second area of the inductor device. The fourth trace is disposed inside the third trace. When the switch is turned off, the first, the second, the third, and the fourth trace form first path. When the switch is turned on, the first, the third, and the fourth trace form second path. The second inductor includes a fifth and a sixth trace. The fifth trace is disposed at the first area of the inductor device. The six trace is disposed at the second area of the inductor device, and coupled to the fifth trace.

Abstract: A wireless communication chip includes an amplifier stage, a first radio frequency circuit, and a second radio frequency circuit. The amplifier stage is configured to receive and amplify a radio frequency signal. The first radio frequency circuit includes a mixer, a baseband transconductor, an output stage, and a switch unit. The mixer is configured to receive an oscillation signal and the radio frequency signal from the amplifier stage, and is configured to adjust a frequency of the radio frequency signal based on the oscillation signal. The switch unit is electrically connected between an input terminal of the baseband transconductor and an output terminal of the baseband transconductor. The first radio frequency circuit and the second radio frequency circuit support different wireless transmission technologies, and are jointly coupled to an output terminal of the amplifier stage.

Abstract: An inductor device includes a first inductor, a switch, and a second inductor. The first inductor includes a first, a second, a third, and a fourth trace. The first trace is disposed at a first area of the inductor device. The second trace is disposed inside the first trace. The third trace is disposed at a second area of the inductor device. The fourth trace is disposed inside the third trace. When the switch is turned off, the first, the second, the third, and the fourth trace form first path. When the switch is turned on, the first, the third, and the fourth trace form second path. The second inductor includes a fifth and a sixth trace. The fifth trace is disposed at the first area of the inductor device. The six trace is disposed at the second area of the inductor device, and coupled to the fifth trace.

Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

Abstract: A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.