Abstract: Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces a predetermined thermal gradient between the first region and the second region.

Abstract: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a semiconductor device. An exemplary method can include removing an oxide from a surface of a first poly layer and forming a second poly layer on the first poly layer in a processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and performing a resist flow operation on the semiconductor substrate after implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the resist flow operation on the semiconductor substrate includes baking the semiconductor substrate in an oven at about 100° C. to about 300° C. for about 5 minutes to about 30 minutes to thin down the resist mask and cause the edges of the resist mask to become rounded.