Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, detect a new task priority for a processor, where the processor is connected to a first node, find a home node for the processor via a cluster to which the processor belongs, and send the new task priority to the home node if the home node is different from the first node. In another embodiment, an interrupt directed to a first processor is detected, the interrupt is determined to be redirectable, a home node for the first process is found via a cluster to which the first processor belongs, and an interrupt vector is sent to the home node if the home node is different from the first node.

Abstract: Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

Abstract: Methods and apparatus are provided that may be utilized to maintain a copy of a processor cache directory on a remote device that may access data residing in a cache of the processor. Enhanced bus transactions containing cache coherency information used to maintain the remote cache directory may be automatically generated when the processor allocates or de-allocates cache lines. Rather than query the processor cache directory prior to each memory access to determine if the processor cache contains an updated copy of requested data, the remote device may query its remote copy.

Abstract: Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.

Abstract: Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.

Abstract: Method and apparatus for supporting interrupt devices configured for a specific architecture (e.g., APIC-based software and hardware) on a different platform (e.g., a PowerPC platform).

Abstract: A sheet transport and aligning apparatus that engages with a sheet to shift the sheet laterally during forward transport of the sheet by a roller. The lateral shift brings the sheet into engagement with a light weight pivotal edge guide which aligns to the sheet to establish a line contact with the sheet as the sheet is driven by the conical drive roller. By continuing to drive the sheet, the sheet pivots with the light weight pivotal edge guide until the sheet is in cross-track and skew alignment.

Abstract: A sheet movement detection system for apparatus having a sheet feed path includes a first capacitor sensor including a first pair of parallel plate members located in opposing relation on opposite sides of the feed path plane at an upstream position and second capacitor sensor including a second pair of parallel plate members, which are correspondingly sized and spaced to said first plate members, in opposing relation on opposite sides of the feed path plane at a downstream position. The sensors are coupled in a detection circuit which applies potentials across the pairs of plate members so that output signals of the first and second sensing means are subtracted from one another. A position circuit detects the output of the detection circuit during movement of a sheet lead edge through the second sensor and provides a sheet lead-edge position signals indicating the position or velocity of the sheet lead edge.

Abstract: An improved sheet-position detection system for apparatus having a sheet feed path and a use location(s). The position detection system includes a first capacitive sensor including a first pair of parallel plate members located in opposing relation on opposite sides of the feed path plane and centered on a desired lead sheet edge position. A second capacitive sensor includes a second pair of parallel plate members that are located in opposing relation on opposite sides of the feed plane and are centered on a desired trail sheet edge position. A bridge circuit applies potentials across the pairs of plate members in a circuit configuration such that output signals of the first and second sensors are subtracted, and when the combined outputs of the first and second sensors is zero, a feed sheet is indicated to be centered between the sensor means.