Abstract: A programmable logic array (PLA) comprising a search array in which the logical AND of one or more inputs (product terms) is formed and coupled to a read array in which each output is formed from a logical OR of one or more of the inputs from the search array. The array has a plurality of output circuits and each output circuit comprises a plurality of physical gates (one gate for each product term input), a common drain diffusion, a load device and an output connection. A plurality of output circuits is formed in each column of the read array and, where circuits overlap so that they cannot be placed in the same column, they are placed in adjacent columns. Where a plurality of outputs share a common product term, gates driven by the same product term are placed in adjacent columns, where they are connected by metal to the common product term ouptut from the search array.

Abstract: Apparatus under microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. It is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. The apparatus also communicates with I/O devices over a demand/response interface.A microprocessor interface with the loop includes loop sync control which establishes bit synchronization and generates a restart pulse at bit receive time and bit send time. The execution of instructions by the microprocessor is stopped and the microprocessor enters a wait state when it has finished all previous work and is ready to receive a loop bit. When it is time to receive the loop bit the microprocessor is restarted in response to the restart pulse from the loop synchronization control.For output operations to a device, the microprocessor loads the device address and a device command or data into shift registers and initiates the transfer by setting a latch.