Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.

Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.

Abstract: A method (200) is disclosed for determining various bit failure modes in a static random access memory device such as may be used in a production test environment to a resolution detailed enough to distinguish between write, read, and disturb failure modes. One method 200 of determining various bit failure modes in an SRAM device, comprises performing a hard/soft bit failure test sequence on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then performing a data retention test on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure to determine whether the cell exhibits a write or disturb failure, and performs a read or disturb test sequence on the cell having write or disturb failure to determine whether the cell exhibits a read or disturb failure.