Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

Abstract: Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel.

Abstract: A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

Abstract: A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a second forward error correction code in response to a change in the indication of the line quality of the second data signal.

Abstract: Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel.

Abstract: A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a second forward error correction code in response to a change in the indication of the line quality of the second data signal.

Abstract: A portable shelter including a shelter body and a lighting system secured to the shelter body. The lighting system includes a lighting system body, at least one light emitter carried by the lighting system body, a power source supplying power to at least one light emitter, and a control circuit controlling at least one light emitter. A remote controller is in wireless communication with the control circuit to control at least one light emitter. Another portable shelter includes a shelter body, at least one lighting cartridge having a cartridge body and at least one light emitter carried by the cartridge body, a power source supplying power to at least one light emitter, and at least one lighting base secured to the shelter body. The lighting base is configured to receive and removably secure the lighting cartridge.

Abstract: A communication connector assembly includes a first connector and a second connector configured to receive the first connector. The first connector includes a first connector body and at least one communication contact supported by the first connector body. The second connector includes a second connector body defining a contact surface configured to receive the first connector and at least one communication contact supported by the second connector body. The communication contact is configured to receive the corresponding communication contact of the first connector. At least one magnet is supported by at least one of the first and second connector bodies and is configured to magnetically retain the first and second connector bodies together.

Abstract: A renewable energy flashlight includes a flashlight housing, a light emitter carried by the housing, and a power source carried by the housing and powering the light emitter. The power source includes a charging magnet, at least one induction coil, and first and second repulsion members, all carried by the housing. The housing is configured to allow movement of the charging magnet between first and second positions within the housing. The induction coil carried is configured to allow movement of the charging magnet therethrough, thereby inducing current through the induction coil. Each repulsion member includes an elastic rebounding material reflexively seeded with at least one internal magnet. The first repulsion member is secured at the first position within the housing in polar opposition to the charging magnet. The second repulsion member secured at the second position within the housing in polar opposition to the charging magnet.

Abstract: A renewable energy flashlight employing a pair of elastomagnetic repulsion members to assist in reciprocating a charging magnet passing through surrounding induction coils to enhance the efficiency of manually charging a capacitor to power an LED lens amplified flashlight.

Abstract: The present invention includes a semiconductor package and a method of making the semiconductor package. The semiconductor package comprises an IC chip and a substrate, wherein part of the substrate routing such as substrate level trace routing is placed on the IC chip using post-passivation thick metal process at wafer level.

Abstract: An integrated circuit package is constructed to potential reduce stress and damage to an integrated circuit die. A rigid transition medium (220) is attached using adhesive layers (215, 42) and interfaces between a tape carrier (260) and the integrated circuit die (210). The integrated circuit package prevents damage such as die cracks and also enhances the service life of the packaged integrated circuit part.

Abstract: A semiconductor package including a universal substrate with interior pads, peripheral pads, and substrate traces positioned between the interior pads and the peripheral pads. The interior pads are configured for electrical interface with a first semiconductor chip. The peripheral pads are configured for electrical interface with a second semiconductor chip that is larger than the first semiconductor chip. By providing a universal substrate that can accommodate multiple die sizes, package design time and costs can thus be reduced.

Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.

Abstract: A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or conductive epoxy through cutouts in the pad. In one embodiment, the cutouts extend into the pad from inner and outer edges thereof. In another embodiment, the cutouts are holes through the pad. A plurality, such as four, capacitors are conveniently disposed atop a corresponding plurality of pads, and are connected to a corresponding plurality of pairs of leads within the semiconductor device assembly. By positioning the capacitor(s) as closely to the semiconductor device as possible, the efficacy of the capacitor(s) is maximized. Method and apparatus are disclosed.

Abstract: A capacitor is disposed within a semiconductor device assembly atop a plastic layer pad, beneath which passes a pair of leads connected to a semiconductor device. The capacitor is connected to the pair of leads, such as by soldering, spot welding or conductive epoxy through cutouts in the pad. In one embodiment, the cutouts extend into the pad from inner and outer edges thereof. In another embodiment, the cutouts are holes through the pad. A plurality, such as four, capacitors are conveniently disposed atop a corresponding plurality of pads, and are connected to a corresponding plurality of pairs of leads within the semiconductor device assembly. By positioning the capacitor(s) as closely to the semiconductor device as possible, the efficacy of the capacitor(s) is maximized. Method and apparatus are disclosed.

Abstract: A first heat sink disposed immediately below and closely adjacent a semiconductor chip in a semiconductor chip assembly is disclosed. The heat sink is a flat metallic or ceramic shim. A second heat sink disposed immediately above and closely adjacent the semiconductor device is disclosed. The second heat sink preferably has a flat surface forming an exterior surface of the semiconductive device assembly . In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications where the semiconductor chip assembly is mounted to a thermal mass. The second heat sink is particularly well-suited to applications where air cooling is available.

Abstract: A semiconductor device assembly is made without a molded package by using a tape having a patterned insulating layer and a conductive layer joined thereto. A semiconductor die is seated on the conductive layer and electrically connected to leads of the patterned conductive layer. A body frame is positioned around the die and electrical leads and connections, and an encapsulant material is distributed over the frame and within the frame over the die and electrical leads and connections.

Abstract: A composite support assembly for an integrated circuit chip includes a rigid lead frame that is attached to a relatively thin flexible tape-like structure. The tape-like structure is etched with inner lead fingers and outer lead fingers to allow a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect an IC chip to the support assembly to be shortened. As a result, a significant increase in the number of leads is realized, using a standard size IC package.