Patents by Inventor Jon M. Long

Jon M. Long has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5304738
    Abstract: After a semiconductor die is placed onto a leadframe and electrically connected to the die, the die and the ends of the leads adjacent to the die are encased in a packaged body. The exposed ends of the leads are trimmed so that the leads are of desired lengths for leadforming, or for connection to substrates or sockets. The ends of the leads are enclosed in a protective body, so that when the package is tested and handled, the protective body reduces undesirable bending of the leads. By trimming the leads before forming the protective body, the leadframe used need not be larger than those normally used.
    Type: Grant
    Filed: March 24, 1993
    Date of Patent: April 19, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5260234
    Abstract: An interconnect structure comprising an interconnection formed between a bond pad and the end of a lead. The layer includes nickel, copper, cobalt, palladium, platinum, silver or gold and is electrically conductive. Also, an apparatus for forming an interconnection by a metal plating process and a device having a lead, a substrate, and a bath containing an aqueous metal plating solution which permits formation of the interconnect structure. A method of forming an interconnect structure including the step of placing a lead adjacent to a bond pad and placing the two in an electroless plating solution so that the interconnect structure may be formed.
    Type: Grant
    Filed: October 9, 1991
    Date of Patent: November 9, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5233131
    Abstract: To bridge the gap between a semiconductor die and the leads of a leadframe, an insulating bridging and support member is used to support the die. The member has thereon conductive traces connected to the die. Provided in the interior portion of the member away from its edges are connecting structures such as holes, slots or grooves. The leads have bent end portions engaging the holes, slots or grooves. The bent end portions are soldered or otherwise connected to the inner surfaces of the holes, slots or grooves by soldering to electrically connect the leads to the traces and to physically attach the member to the leadframe. The above-described structure permits the bonding sites between adjacent leads to the member to be greater than lead spacing of the leadframe. The leads are in the shape of elongated rods of uniform cross-section to maximize the lead density possible around the bridging and support member.
    Type: Grant
    Filed: September 16, 1991
    Date of Patent: August 3, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Louis H. Liang, Jon M. Long
  • Patent number: 5221812
    Abstract: After a semiconductor die is placed onto a leadframe and electrically connected to the die, the die and the ends of the leads adjacent to the die are encased in a packaged body. The exposed ends of the leads are trimmed so that the leads are of desired lengths for leadforming, or for connection to substrates or sockets. The ends of the leads are enclosed in a protective body, so that when the package is tested and handled, the protective body reduces undesirable bending of the leads. By trimming the leads before forming the protective body, the leadframe used need, not be larger than those normally used.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: June 22, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5218215
    Abstract: A semiconductor device package is disclosed which facilitates the dissipation of heat generated by the enclosed semiconductor device. The package comprises a housing apparatus having a plurality of portions, a holding apparatus having a semiconductor device thermally attached, a thermal path formed within at least one of the portions of the housing apparatus, and a thermally conductive connection for thermally connecting the holding apparatus to the thermal path. The portions of the housing apparatus join together to form an enclosed chamber which encases the holding apparatus, the semiconductor device, and the thermally conductive connection. The thermal path thermally connects the interior of the package to the external environment. By thermally connecting the holding apparatus to the thermal path formed within the housing apparatus, a direct thermal path is created between the device and the external environment so that heat from the device may readily escape from the interior of the package.
    Type: Grant
    Filed: December 19, 1990
    Date of Patent: June 8, 1993
    Assignee: VLSI Technology, Inc.
    Inventors: Louis Liang, Jon M. Long
  • Patent number: 5210375
    Abstract: The exposed portions of the leads of a semiconductor chip package are first bent in a forming process so that the ends of the leads are in proper positions to be attached to and electrically connected to contacts on a printed circuit board. Intermediate portions of the leads between the distal ends and the package body for connection to the printed circuit board and the package body are enclosed and fixed in position by a carrier body to hold the leads in position and to reduce the effects of any bending in destroying the coplanarity of the distal lead ends of the package. The package with the carrier body may be mounted onto the printed circuit board without first removing the carrier body. After the distal ends of the leads have been soldered to the printed circuit board, the carrier body is then removed.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: May 11, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5210440
    Abstract: A novel semiconductor chip cooling apparatus includes at least one semiconductor die packaged according to a TAB design. A support structure supports the die, and a dike is connected to the support structure and the TAB tape to form a cavity impervious to liquid and air. Input and output means are connected to the cavity. Fluid means circulate throughout the cavity and utilize the input and output means to directly cool the die during operation of the semiconductor die. Heat spreading means may be positioned below the die to increase the amount of surface area which contacts the fluid means, thereby cooling the die more efficiently.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: May 11, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5206794
    Abstract: A molded, plastic integrated circuit package is formed wherein a silicone compound is first applied over the exposed surface of the integrated circuit, its bonding wires, and portions of the lead frame including those portions where the bonding wires are attached. Following application of the silicone compound and before molding in plastic, the silicone compound is cured to set and harden the material. With the bonding wires and bonding points thus encapsulated by the silicone compound, the bonding wires are protected from lateral bending forces caused by viscous forces during the process of forming the molded plastic package, and from longitudinal expansion and contraction forces during thermal temperature cycling of the package.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: April 27, 1993
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5173766
    Abstract: A semiconductor device package and a method of making such a package is described. The package comprises a flexible packaging substrate having a patterned metal layer onto which a semiconductor die is attached and a patterned insulative layer attached to the metal layer. The insulative layer includes an annular epoxy-seal gap. A glob of silicone gel is deposited and cured on the die. A casting frame is connected to the metal layer of the flexible substrate on the same side as the die. A backside moisture-blocking layer of material is attached to an opposed side of the tape. The frame and the backside layer are attached to the metal layer of the flexible substrate using cross-linkable epoxy adhesives. These epoxy adhesives join through the epoxy-seal gap to define an epoxy-seal around the die. A thermoset type of molding compound is then poured into the casting frame to define a moisture resistant package body.
    Type: Grant
    Filed: June 25, 1990
    Date of Patent: December 22, 1992
    Assignee: LSI Logic Corporation
    Inventors: Jon M. Long, Rachel S. Sidorovsky, Michael J. Steidl, Adrian Murphy, Bidyut Sen
  • Patent number: 5166607
    Abstract: A method and apparatus are disclosed for burning-in semiconductor devices. The method includes the steps of: (1) heating the surface of the semiconductor device; (2) cooling the leads of the semiconductor device package so as to maintain the temperature of the outer portions of the leads at, near, or below room temperature; and optionally (3) causing circuits on the semiconductor device to operate electrically while it is being heated. An apparatus for implementing the aforementioned method is also disclosed. In a first embodiment, the apparatus comprises a base plate for heating the surface of the semiconductor device, a cooling plate for cooling the leads of the semiconductor device package, and optionally an electrical testing device for causing the semiconductor device to operate electrically during the heating process.
    Type: Grant
    Filed: May 31, 1991
    Date of Patent: November 24, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Jon M. Long
  • Patent number: 5023202
    Abstract: An improved method to assemble tape packaged integrated circuits includes spot welding a strip of TAB tape to a thin strip of copper called a strip carrier. The strip carrier provides mechanical rigidity to the tape during later processing, including die attachment and lead bonding and solder plating, as well as providing ESD protection since each tape lead is shorted to the strip carrier. The packaged die and the surrounding tape are excised from the strip carrier prior to final testing and the strip carrier is capable of being reused. The strip carriers are of a size and shape to be readily handled by existing integrated circuit handling equipment.
    Type: Grant
    Filed: July 14, 1989
    Date of Patent: June 11, 1991
    Assignee: LSI Logic Corporation
    Inventors: Jon M. Long, Michael J. Steidl