Patents by Inventor Jon Martens

Jon Martens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11624764
    Abstract: Improved coaxial connectors and methods which have enhanced characteristics, reliability, strength, and durability. This coaxial connector system uses a flange mating system and a single slot male pin center conductor contact. The flanges use precision guiding pins and screws to axially align and secure the mating flanges together. The coaxial center conductors are electrically connected to each other by a resilient, single slotted, formed male pin and a female receptacle as center conductor assemblies. When the two flanges are fastened together, the center conductor assemblies (formed male pin and a female receptacle) mate to form an electrically conducting connection.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 11, 2023
    Assignee: Anritsu Company
    Inventors: Thomas H Roberts, Jon Martens, Jim Mallette, Anthony Vega
  • Patent number: 11558129
    Abstract: Systems and methods for calibrating VNA modules which dynamically assigns match utilization to improve overall calibration accuracy and reduce problems from a non-optimal set of calibration components and simplify user input requirements during calibration.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: January 17, 2023
    Assignee: Anritsu Company
    Inventors: Jon Martens, Gary Chock, Jamie Tu, Elena Vayner, Amruth Sai Gandavarapu, Mrunal Damle
  • Patent number: 11237197
    Abstract: A system and method for making improved measurements of integrated antenna arrays utilizes vector network analyzer (VNA) and a calibrated receive-side system comprising two antennae, dual reflectometers coupled to the two antennae for match correction, a wide band intermediate frequency (IF) strip which connects the receive-side system to the input ports of the VNA, an air gap which separates the receive-side system form the DUT, and a stepmotion baffle configure to be inserted into the air gap to modify antenna coupling. The system and method enable measurement of noise characteristics of the DUT including nonlinear effects of transmitter element coupling between the plurality of transmitter elements within an antenna array.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: February 1, 2022
    Assignee: ANRITSU COMPANY
    Inventor: Jon Martens
  • Patent number: 11121514
    Abstract: A coaxial connector system is provided suitable for connection of high-frequency components such as high-band test modules and probes. The coaxial connector system uses a flange mating element aligned using precession guiding pins. A center conductor assembly is captive in a center bore of the flange and includes elastomer contacts which are compressed against the coaxial center conductors of the high=frequency components. The flange mount coaxial connector system provides a robust, mechanically stable mount which minimizes electrical performance changes with mechanical torque as compared to screw on connectors.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 14, 2021
    Assignee: ANRITSU COMPANY
    Inventors: Thomas H Roberts, Jon Martens
  • Patent number: 10634757
    Abstract: A harmonic phase standard includes an input connectable with a radio frequency (RF) signal source for receiving an RF signal, an output, a signal path extending between the input and the output for propagating the RF signal from the input to the output, and a logic gate, an amplifier and a nonlinear transmission line (NLTL) arranged along the signal path. The logic gate receives the RF signal and outputs a waveform having sharpened edges relative to the RF signal. The amplifier amplifies the waveform output by the logic gate. The NLTL receives the amplified waveform from the amplifier and is biased to shape the amplified waveform so as to add harmonic content to the amplified waveform.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: April 28, 2020
    Assignee: ANRITSU COMPANY
    Inventors: Jon Martens, Karam Noujeim
  • Patent number: 10481178
    Abstract: A method for marking relevant data within an acquired set of data in accordance with an embodiment includes receiving a location of a first synchronization event within a synchronizing time pulse synchronized with the acquired set of data, searching the synchronizing time pulse within a predetermined window for the first synchronization event based on the location, identifying the first synchronization event based on the search, and obtaining data from the acquired set of data within an offset range determined based on the identified first synchronization event. The steps are then iteratively repeated for a number of periods.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: November 19, 2019
    Assignee: ANRITSU COMPANY
    Inventors: Jon Martens, David Judge, Jamie Tu
  • Patent number: 8718586
    Abstract: Shockline-based samplers of a vector-network analyzer (VNA) have enhanced dynamic range by using a dynamic bias network applied to the non-linear transmission lines (NLTLs) or shocklines. The bias voltage applied to the NLTL provides direct control over the falling-edge shockline compression, and thus the insertion loss and overall RF bandwidth of the sampler. Alternating between a forward bias voltage to turn off a shockline sampler when it is not needed and thereby reducing spurious generation and improving isolation can be alternatively applied with a reverse bias voltage to turn on the shockline sampler in a normal operation mode. By measuring the shockline output and providing feedback in the reverse-bias mode, the bias voltage can be dynamically adjusted to significantly increase the performance of the NLTL based sampler. In the presence of a strong positive bias voltage, the incoming LO and its harmonics experience large ohmic losses thus preventing gating pulses from forming in the shockline.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: May 6, 2014
    Assignee: Anritsu Company
    Inventors: Jon Martens, Karam Michael Noujeim
  • Patent number: 8630591
    Abstract: Systems and methods are provided for calibrating a receiver in an RF system having a device under test (DUT) configured to receive at least one input signal and output at least one response signal. A method comprises setting a drive level of the RF system and making a pair of measurements at the drive level. Each of the measurements is made in a different gain state at a receiver. The method also comprises calculating a calibration factor for the receiver which is a ratio of the pair of measurements. These systems and methods can be used to calibrate receivers while preserving vector information and removing dynamic match effects.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: January 14, 2014
    Assignee: Anritsu Company
    Inventors: Jon Martens, Thomas Albrecht
  • Publication number: 20100330944
    Abstract: Shockline-based samplers of a vector-network analyzer (VNA) have enhanced dynamic range by using a dynamic bias network applied to the non-linear transmission lines (NLTLs) or shocklines. The bias voltage applied to the NLTL provides direct control over the falling-edge shockline compression, and thus the insertion loss and overall RF bandwidth of the sampler. Alternating between a forward bias voltage to turn off a shockline sampler when it is not needed and thereby reducing spurious generation and improving isolation can be alternatively applied with a reverse bias voltage to turn on the shockline sampler in a normal operation mode. By measuring the shockline output and providing feedback in the reverse-bias mode, the bias voltage can be dynamically adjusted to significantly increase the performance of the NLTL based sampler. In the presence of a strong positive bias voltage, the incoming LO and its harmonics experience large ohmic losses thus preventing gating pulses from forming in the shockline.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: ANRITSU COMPANY
    Inventors: Jon Martens, Karam Michael Noujeim
  • Patent number: 7068046
    Abstract: Embodiments of the present invention are directed towards systems, methods, and computer readable media for performing multiport vector network analysis. Embodiments of the present invention relate to a multiport network analysis that is derived from a family of two port calibration techniques including Thru/Reflect/Line (TRL), Thru/Reflect/Match (TRM), Line/Reflect/Line (LRL), Line/Reflect/Match (LRM) and several others. An improved calibration method enables the use of a simplified switch matrix to perform accurate vector network analysis in communications and networking systems. After determining some characteristics through conventional methods, a two tier load match correction is performed on the results. The improved correction mechanism enables the system to perform comparably to systems with more complicated switch matrices.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: June 27, 2006
    Assignee: Anritsu Company
    Inventors: Jon Martens, David Judge, Jimmy Bigelow
  • Publication number: 20060103392
    Abstract: Embodiments of the present invention are directed towards systems, methods, and computer readable media for performing multiport vector network analysis. Embodiments of the present invention relate to a multiport network analysis that is derived from a family of two port calibration techniques including Thru/Reflect/Line(TRL), Thru/Reflect/Match(TRM), Line/Reflect/Line (LRL), Line/Reflect/Match (LRM) and several others. An improved calibration method enables the use of a simplified switch matrix to perform accurate vector network analysis in communications and networking systems. After determining some characteristics through conventional methods, a two tier load match correction is performed on the results. The improved correction mechanism enables the system to perform comparably to systems with more complicated switch matrices.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Applicant: Anritsu Company
    Inventors: Jon Martens, David Judge, Jimmy Bigelow
  • Patent number: 6714898
    Abstract: An instrument is provided for measuring a noise figure with significant flexibility. The instrument includes a noise source (306) and a vector network analyzer (VNA) (300). The VNA (300) includes an external connector port (302) for removable connection of the noise source (306). The noise source (306) can be connected to the VNA backplane port (302), or directly to a DUT (350). The DUT (350) can be connected to both VNA test ports (310,314) if the noise source (306) is connected to port (302), or only to test port (314) if the noise source (306) is directly connected to the DUT. A receiver connected to the test port (314) includes a downconverter (324) providing an IF signal through either a narrowband IF channel (350) or a wideband IF channel (352) for providing both wideband and narrowband power measurements enabling fast accurate measurement of a noise figure.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: March 30, 2004
    Assignee: Anritsu Company
    Inventors: Peter Kapetanic, Jon Martens, David Rangel
  • Patent number: 6529844
    Abstract: A vector network analyzer (VNA) is provided with three test ports and an integration of hardware and software to make an integrated set of measurements for two and three port devices. The integrated capability allows for fast, versatile measurements that benefits, in accuracy and convenience, from sharing of data and resources with other measurements. The VNA includes a first signal source which is selectively connectable through reflectometers to two of the three VNA test ports. A second signal source provides connection through a third reflectometer to a third test port to enable full vector error corrected 3-port S-parameters measurements to be made. The two signal sources, along with software configuration of the VNA to operate in a non-ratioed mode provides for measuring second and third order intercept measurements. The two signal sources and software also enable the VNA to be used to make frequency translation measurements of a mixer including accurate frequency translation group delay measurements.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: March 4, 2003
    Assignee: Anritsu Company
    Inventors: Peter Kapetanic, Jon Martens, David Rangel
  • Patent number: 6396287
    Abstract: A method is provided for eliminating the source harmonic component from VNA measurements of the output of a device under test (DUT). A standard vector measurement, GHx, is first measured from the DUT using the VNA. The value GHx is composed of two elements, the DUT's harmonic response to a fundamental input from the source, and the DUT's linear response to the harmonic input from the source. The harmonics from the source which are linearly passed by the DUT, GNx, are then measured with the VNA. The output harmonic generated by the DUT, Hx, is then calculated using vector subtraction according to the equation Hx=GHx−GNx. The output harmonic Hx will then be free from source harmonic components.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: May 28, 2002
    Assignee: Anritsu Company
    Inventors: Peter Kapetanic, Jon Martens, David Rangel
  • Patent number: 6316945
    Abstract: A method for determining the harmonic response of a device under test (DUT) to the input fundamental frequency component of an input signal is performed on a vector network analyzer. A first response of the DUT at the harmonic frequency is obtained by measuring the linear response of the device at the harmonic frequency of interest after appropriate normalization. A second response of the DUT is obtained by measuring the response of the DUT at the harmonic frequency to an input which comprises a source input fundamental with its harmonic components after appropriate normalization. The harmonic response of the DUT to the source input fundamental alone is computed from the first and second responses. Such computations allow the harmonic response of the DUT to be measured free of stimulus source harmonics, so that overall harmonic measurement accuracy and dynamic range is enhanced.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: November 13, 2001
    Assignee: Anritsu Company
    Inventors: Peter Kapetanic, Jon Martens, David Rangel
  • Patent number: 6292000
    Abstract: A method for determining the harmonic phase response ∠POx of a device under test (DUT) is performed on a vector network analyzer (VNA). The phase ∠GN1 of the transfer response GN1 of the DUT at the fundamental frequency is determined from VNA measurements after appropriate normalization. The corrected phase ∠GHxC of the harmonic transfer response of the DUT is determined from VNA measurements after appropriate normalization. The corrected phase ∠GHxC of the harmonic transfer coefficient GHx is subtracted from a predetermined phase reference ∠refx to obtain a difference ∠refx−∠GHxC, and the phase ∠GN1 of the transfer coefficient GN1 at the fundamental frequency is added to the difference ∠refx−∠GHxC to obtain the harmonic phase offset ∠POx. For the second and third harmonics using a clipping waveform, the phase reference ∠refx is 180°.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: September 18, 2001
    Assignee: Anritsu Company
    Inventors: Peter Kapetanic, Jon Martens, David Rangel