Patents by Inventor Jon N. Hasselgren

Jon N. Hasselgren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11748843
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 5, 2023
    Assignee: INTEL CORPORATION
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Patent number: 11574383
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Publication number: 20220335569
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: February 22, 2022
    Publication date: October 20, 2022
    Inventors: Tomas G. AKENINE-MOLLER, Robert M. TOTH, Bjorn JOHNSSON, Jon N. HASSELGREN
  • Patent number: 11361498
    Abstract: A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Jacob J. Munkberg, Franz Petrik Clarberg, Tomas G. Akenine-Moller
  • Patent number: 11263725
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Patent number: 11222462
    Abstract: A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Jacob J. Munkberg, Franz Petrik Clarberg, Tomas G. Akenine-Moller
  • Publication number: 20210350502
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: May 25, 2021
    Publication date: November 11, 2021
    Inventors: Tomas G. AKENINE-MOLLER, Robert M. TOTH, Bjorn JOHNSSON, Jon N. HASSELGREN
  • Patent number: 11024007
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Publication number: 20210012457
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Tomas G. AKENINE-MOLLER, Robert M. TOTH, Bjorn JOHNSSON, Jon N. HASSELGREN
  • Patent number: 10776994
    Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg
  • Patent number: 10733695
    Abstract: Embodiments described herein enable a hierarchical-Z unit of a graphics processor to be primed using Hi-Z data generated by occlusion culling operations performed on a general purpose processor. One embodiment provides for instructions to cause operations including performing occlusion culling for a scene via the general purpose processor and storing generated hierarchical-Z data. The Hierarchical-Z data generated during the occlusion culling operations can be shared with the graphics processor and used to prime a hierarchical-Z unit of the graphics processor. The at least a portion of the scene can then be rendered using the hierarchical-Z data after priming the hierarchical-Z unit, improving the effectiveness of hierarchical-Z operations of the graphics processor for the scene.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: Magnus Andersson, Jon N. Hasselgren, Tomas G. Akenine-Moller
  • Patent number: 10621691
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described. In one example, compression in graphics rendering may include determining a plurality of color values associated with individual pixels of a tile of pixels, generating a subset of the plurality of color values such that the subset of the plurality of color values include one or more distinct color values from the plurality of color values, associating an index value with each color value of the subset of the plurality of color values, determining, for each of the individual pixels, an associated pixel index value to generate a plurality of pixel index value associated with the individual pixels of the tile of pixels, storing, in memory, graphics data including the subset of the plurality of color values, the associated index values, and the plurality of pixel values.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim. K. Nilsson
  • Patent number: 10540808
    Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Magnus Andersson, Robert M. Toth, Jon N Hasselgren, Tomas G. Akenine-Moller
  • Publication number: 20190347764
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Tomas G. AKENINE-MOLLER, Robert M. TOTH, Bjorn JOHNSSON, Jon N. HASSELGREN
  • Patent number: 10466769
    Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Bjorn Johnsson, Magnus Andersson, Jim K. Nilsson, Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 10453170
    Abstract: Methods and apparatus relating to techniques for provision of minimum or maximum and bitwise logic AND or logic OR based coarse stencil tests are described. In an embodiment, metadata (corresponding to a plurality of pixels) is stored in memory. One or more operations are performed on the metadata to generate a stencil result. The one or more operations comprise a bitwise intersection operation or a bitwise union operation and/or a minimum operation or maximum operation. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Carl J. Munkberg, Jon N. Hasselgren
  • Patent number: 10445859
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Patent number: 10380789
    Abstract: An apparatus and method are described for performing an efficient depth prepass. For example, one embodiment of a method comprising: a method comprising: performing a first pass through a specified portion of a graphics pipeline with only depth rendering active; initializing a coarse depth buffer within the specified portion of the graphics pipeline during the first pass, the coarse depth buffer storing depth data at a level of granularity less than that stored in a per-pixel depth buffer, which is not initialized during the first pass; and performing a second pass through the graphics pipeline following the first pass, the second pass utilizing the full graphics pipeline and using values in the coarse depth buffer initialized by the first pass.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Magnus Andersson, Tomas G. Akenine-Moller, Jon N. Hasselgren
  • Patent number: 10373370
    Abstract: A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Jacob J. Munkberg, Franz Petrik Clarberg, Tomas G. Akenine-Moller
  • Patent number: 10354432
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Jon N. Hasselgren, Franz P. Clarberg, Magnus Andersson, Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Moller