Abstract: Methods for forming silicon containing films using silylamine moieties are disclosed. In some embodiments, silylamine moieties are employed to deposit silicon-nitrogen, silicon-oxygen, or silicon-nitrogen-oxygen materials at temperatures of less than 550° C. In some embodiments methods are practiced within process chambers adapted to contain a single substrate as well as within process chambers adapted to contain a plurality of substrates, where the silylamine moieties are conveyed to the chambers in across flow type manner.

Abstract: The present invention provides systems and methods for forming a multi-layer, multi-component high-k dielectric film. In some embodiments, the present invention provides systems and methods for forming high-k dielectric films that comprise hafnium, titanium, oxygen, nitrogen, and other components. In a further aspect of the present invention, the dielectric films are formed having composition gradients.

Abstract: A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e.

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e.