Abstract: The current invention uses a combination of technologies from dye-sensitized solar cells, and from thermionic generators, to form a unique, efficient, broad spectrum solar radiation to electric power converter. Light passing through the cell first passes through a dye-sensitized matrix of nanoporous semiconductor. Light within the absorption spectrum of the dye is absorbed and converted into electrons which are injected into the conduction band of the semiconductor matrix. Light, which is not absorbed by the dye, passes on to cathode. The cathode is heated upon absorbing the incoming radiation. At a temperature dependent on the work function of the cathode, the cathode emits electrons thermionically, thereby cooling the cathode. These electrons replenish the electrons in the dye, thus completing the flow of current between cathode and anode. The hot cathode is thermally isolated from portions of the device at ambient temperature, thereby minimizing parasitic thermal loss.

Abstract: A reciprocating internal combustion engine is based on Homogenous Charge Compression Ignition (HCCI) that occurs in a deformable, resonant combustion chamber and that is coupled mechanically to efficient, resonant, electro-mechanical transducers acting as motors and generators. The mechanical coupling also implements fuel/air intake valves and exhaust valves. Embedded sensors allow an electronic control system to start the engine and thereafter to maintain operational configuration of the moving components in response to the effects of imperfect mechanical fabrication and/or assembly and dynamic changes in mechanical properties of the materials with run-time temperature and engine life.

Abstract: A reciprocating internal combustion engine is based on Homogenous Charge Compression Ignition (HCCI) that occurs in a deformable, resonant combustion chamber and that is coupled mechanically to efficient, resonant, electromechanical transducers acting as motors and generators. The mechanical coupling also implements fuel/air intake valves and exhaust valves. Embedded sensors allow an electronic control system to start the engine and thereafter to maintain operational configuration of the moving components in response to the effects of imperfect mechanical fabrication and/or assembly and dynamic changes in mechanical properties of the materials with run-time temperature and engine life.

Abstract: A reciprocating internal combustion engine is based on Homogenous Charge Compression Ignition (HCCI) that occurs in a deformable, resonant combustion chamber and that is coupled mechanically to efficient, resonant, electro-mechanical transducers acting as motors and generators. The mechanical coupling also implements fuel/air intake valves and exhaust valves. Embedded sensors allow an electronic control system to start the engine and thereafter to maintain operational configuration of the moving components in response to the effects of imperfect mechanical fabrication and/or assembly and dynamic changes in mechanical properties of the materials with run-time temperature and engine life.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A resistor circuit includes a resistance control circuit and at least one insulated gate field effect transistor. The resistance control circuit includes a control signal output element including a reference transistor for generating a resistance control signal in response to an internal control signal to maintain the reference transistor at a selected resistance value and a resistance value control element including a reference resistor for generating a circuit control signal for controlling the resistance value of the reference transistor in relation to the resistance value provided by the reference resistor. The field effect transistor is controlled by the resistance control signal to provide a resistance value which is a function of the resistance value of the reference transistor (and therefore of the reference resistor) and ratios of selected physical characteristics of the reference transistor.

Abstract: A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal.

Abstract: A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

Abstract: A content addressable memory cell comprises two storage IGFETs connected between a Match line and respective bitlines. Stored potentials are applied to the gates of the IGFETs through Write IGFETs which are cross coupled to the bitlines. The cross-coupling results in a larger storage capacitance and reduced degenerative capacitive coupling. This improves the speed and noise immunity of the cell. The memory cell is fabricated with three primary levels: a lower level of semiconductor material in which the source, drain and channel of each FET is formed, a center level of conductive material in which the Match and Write lines and the gates of the FETs are formed and an upper level in which the bitlines are formed. The center and lower levels are interconnected at buried contacts.

Abstract: A content addressable memory cell includes two storage field effect transistors of opposite conductivity type with their gates connected in common. A single write transistor is connected between the common gates and a bitline for storing a potential on the gates from the bitline.

Abstract: In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node.