Patents by Inventor Jon Robert Berry
Jon Robert Berry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230418581Abstract: Using a common reference address when processing calls between a native application binary interface (ABI) and a foreign ABI. Based on a caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code and that the callee is native, or a memory range not storing native code and that the callee is foreign. Execution of a callee is initiated based on one of (i) calling the callee using the reference address within an emulator when the caller is native and the callee is foreign; (ii) calling an entry thunk when the caller is foreign and the callee is native; (iii) calling an exit thunk when the caller is native and the callee is foreign; or (iv) directly calling the callee using the reference address when the caller is native and the callee is native.Type: ApplicationFiled: June 13, 2023Publication date: December 28, 2023Inventors: Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Darek Josip MIHOCKA, Jon Robert BERRY, Russell Charles HADLEY, James David CLEARY, Clarence Siu Yeen DANG
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Patent number: 11720335Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.Type: GrantFiled: December 14, 2021Date of Patent: August 8, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Russell Charles Hadley, James David Cleary, Clarence Siu Yeen Dang
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Patent number: 11403100Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.Type: GrantFiled: August 31, 2020Date of Patent: August 2, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Darek Josip Mihocka, Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James David Cleary, Jon Robert Berry, YongKang Zhu, Tiansheng Tan
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Patent number: 11366666Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.Type: GrantFiled: August 31, 2020Date of Patent: June 21, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Darek Josip Mihocka, Clarence Siu Yeen Dang, Pedro Miguel Sequeira De Justo Teixeira, Pavlo Lebedynskiy, James David Cleary, Jon Robert Berry, YongKang Zhu, Tiansheng Tan
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Publication number: 20220137942Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.Type: ApplicationFiled: December 14, 2021Publication date: May 5, 2022Inventors: Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Darek Josip MIHOCKA, Jon Robert BERRY, Russell Charles HADLEY, James David CLEARY, Clarence Siu Yeen DANG
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Publication number: 20220066780Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Darek Josip MIHOCKA, Clarence Siu Yeen DANG, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA, Pavlo LEBEDYNSKIY, James David CLEARY, Jon Robert BERRY, YongKang ZHU, Tiansheng TAN
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Patent number: 11231918Abstract: A function is compiled against a first application binary interface (ABI) and a second ABI of a native first instruction set architecture (ISA). The second ABI defines context data not exceeding a size expected by a third ABI of a foreign second ISA, and uses a subset of registers of the first ISA that are mapped to registers of the second ISA. Use of the subset of registers by the second ABI results in some functions being foldable when compiled using both the first and second ABIs. First and second compiled versions of the function are identified as foldable, or not, based on whether the compiled versions match. Both the first and second compiled versions are emitted into a binary file when they are not foldable, and only one of the first or second compiled versions is emitted into the binary file when they are foldable.Type: GrantFiled: August 31, 2020Date of Patent: January 25, 2022Assignee: MICROSOFT TECHNOLOGLY LICENSING, LLCInventors: Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Russell Charles Hadley, James David Cleary, Clarence Siu Yeen Dang
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Patent number: 11042422Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. When executing in a compatibility process, the EC code stream can interact with a foreign code stream that executes in an emulator. The foreign code stream can be included in the hybrid binary itself, or can be external to the hybrid binary. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.Type: GrantFiled: August 31, 2020Date of Patent: June 22, 2021Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Pavlo Lebedynskiy, Pedro Miguel Sequeira De Justo Teixeira, Darek Josip Mihocka, Jon Robert Berry, Clarence Siu Yeen Dang, Tiansheng Tan, James David Cleary, Yongkang Zhu, Theodore Maxwell Thomas, Ben Niu, Russell Charles Hadley
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Patent number: 10339295Abstract: A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.Type: GrantFiled: July 28, 2016Date of Patent: July 2, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Jon Robert Berry, Youssef Barakat, Yevgeniy M. Bak, Mehmet Iyigun, Pedro Miguel Sequeira de Justo Teixeira
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Patent number: 10088892Abstract: Controlling background activity in a computing device or system during a low-power mode is described. In some example techniques, when a computing device or system is in a low power mode, a determination is made whether to block one or more trigger events from causing an activation of one or more respective background task operations. Based at least in part on the determination, at least one trigger event may be allowed to cause an activation of a respective background task operation during the low power mode.Type: GrantFiled: March 21, 2016Date of Patent: October 2, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Hari Pulapaka, Alain Gefflaut, Jon Robert Berry, Emily Wilson, Qian Liu
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Publication number: 20180032378Abstract: A computing system includes one or more processors and a storage device that stores computer executable instructions that can be executed by the processors to cause the computing system to perform the following. The system generates a work tracking information ticket for a first system entity. The system assigns the work tracking information ticket to the first system entity. The system passes the work tracking information ticket to one or more second system entities. The system validates the work tracking information ticket. The validated work tracking information ticket informs that the one or more second system entities are performing work on behalf of the first system entity.Type: ApplicationFiled: July 28, 2016Publication date: February 1, 2018Inventors: Jon Robert Berry, Youssef Barakat, Yevgeniy M. Bak, Mehmet lyigun, Pedro Miguel Sequeira de Justo Teixeira
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Publication number: 20160202750Abstract: Controlling background activity in a computing device or system during a low-power mode is described. In some example techniques, when a computing device or system is in a low power mode, a determination is made whether to block one or more trigger events from causing an activation of one or more respective background task operations. Based at least in part on the determination, at least one trigger event may be allowed to cause an activation of a respective background task operation during the low power mode.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Inventors: Hari Pulapaka, Alain Gefflaut, Jon Robert Berry, Emily Wilson, Qian Liu
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Patent number: 9292080Abstract: Controlling background activity in a computing device or system during a low-power mode is described. In some example techniques, when a computing device or system is in a low power mode, a determination is made whether to block one or more trigger events from causing an activation of one or more respective background task operations. Based at least in part on the determination, at least one trigger event may be allowed to cause an activation of a respective background task operation during the low power mode.Type: GrantFiled: June 19, 2013Date of Patent: March 22, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Hari Pulapaka, Alain Gefflaut, Jon Robert Berry, Emily Wilson, Qian Liu
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Publication number: 20140380075Abstract: Controlling background activity in a computing device or system during a low-power mode is described. In some example techniques, when a computing device or system is in a low power mode, a determination is made whether to block one or more trigger events from causing an activation of one or more respective background task operations. Based at least in part on the determination, at least one trigger event may be allowed to cause an activation of a respective background task operation during the low power mode.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: Hari Pulapaka, Alain Gefflaut, Jon Robert Berry, Emily Wilson, Qian Liu