Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 ?m between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.