Patents by Inventor Jon Slaughter

Jon Slaughter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160180911
    Abstract: Circuitry and methods provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a charging pulses of opposite polarity in comparison with write pulses. The charging pulse of opposite polarity may comprise equal or different width and amplitude than that of the write pulse, may be applied with each write pulse or a series of write pulses, and may be applied prior to or subsequent to the write pulse. A register is also used to keep track of the read pulse polarity such that read pulses of alternating polarity can be used in reading operations.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Inventors: Michael Schneider, Dimitri Houssameddine, Jon Slaughter
  • Publication number: 20160172582
    Abstract: A magnetoresistive memory array including a plurality of magnetoresistive memory elements wherein each magnetoresistive memory element comprises a free layer including at least one ferromagnetic layer having perpendicular magnetic anisotropy, a fixed layer, and a tunnel barrier, disposed between and in contact with the free and fixed layers. The tunnel barrier includes a first metal-oxide layer, having a thickness between 1 and 10 Angstroms, a second metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed on the first metal-oxide layer, and a third metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed over the second metal-oxide layer. In one embodiment, the third metal-oxide layer is in contact with the free layer or fixed layer. The tunnel barrier may also include a fourth metal-oxide layer, having a thickness between 1 and 10 Angstroms, disposed between the second and third metal-oxide layers.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 16, 2016
    Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
  • Publication number: 20160163964
    Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Publication number: 20160163962
    Abstract: A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Phillip MATHER, Jon SLAUGHTER, Nicholas RIZZO
  • Patent number: 9362491
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 7, 2016
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Publication number: 20160104835
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Application
    Filed: November 30, 2015
    Publication date: April 14, 2016
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu WHIG, Phillip MATHER, Kenneth SMITH, Sanjeev AGGARWAL, Jon SLAUGHTER, Nicholas RIZZO
  • Publication number: 20160104519
    Abstract: Techniques and circuits for storing and retrieving data using spin-torque magnetic memory cells as anti-fuses are presented. Circuits are included to allow higher-magnitude voltages and currents to be applied to magnetic memory cells to intentionally break down the dielectric layer included the magnetic tunnel junction. Magnetic memory cells having a normal-resistance magnetic tunnel junction with an intact dielectric layer are used to store a first data state, and magnetic memory cells having a magnetic tunnel junction with a broken-down dielectric layer are used to store a second data state. Data can be stored in such a manner during wafer probe and then later read out directly or copied into other magnetic or non-magnetic memory on the device for use in operations after the device is included in a system.
    Type: Application
    Filed: October 8, 2015
    Publication date: April 14, 2016
    Inventors: Jon Slaughter, Jason Allen Janesky
  • Publication number: 20160093349
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
  • Publication number: 20160093354
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Publication number: 20160084920
    Abstract: A magnitude and direction of at least one of a reset current and a second stabilization current (that produces a reset field and a second stabilization field, respectively) is determined that, when applied to an array of magnetic sense elements, minimizes the total required stabilization field and reset field during the operation of the magnetic sensor and the measurement of the external field. Therefore, the low field sensor operates optimally (with the highest sensitivity and the lowest power consumption) around the fixed external field operating point. The fixed external field is created by other components in the sensor device housing (such as speaker magnets) which have a high but static field with respect to the low (earth's) magnetic field that describes orientation information.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 24, 2016
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Lianjun LIU, Phillip MATHER, Jon SLAUGHTER
  • Patent number: 9293698
    Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: March 22, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
  • Patent number: 9286963
    Abstract: Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied with each write pulse or a series of write pulses, and may be applied prior to or subsequent to the write pulse.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 15, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Michael Schneider, Dimitri Houssameddine, Jon Slaughter
  • Patent number: 9276200
    Abstract: A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: March 1, 2016
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Phillip Mather, Jon Slaughter, Nicholas Rizzo
  • Publication number: 20160055894
    Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.
    Type: Application
    Filed: April 27, 2015
    Publication date: February 25, 2016
    Inventors: Dimitri Houssameddine, Jon Slaughter
  • Patent number: 9269891
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 23, 2016
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Philip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Publication number: 20160013401
    Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.
    Type: Application
    Filed: September 21, 2015
    Publication date: January 14, 2016
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Patent number: 9229070
    Abstract: A magnitude and direction of at least one of a reset current and a second stabilization current (that produces a reset field and a second stabilization field, respectively) is determined that, when applied to an array of magnetic sense elements, minimizes the total required stabilization field and reset field during the operation of the magnetic sensor and the measurement of the external field. Therefore, the low field sensor operates optimally (with the highest sensitivity and the lowest power consumption) around the fixed external field operating point. The fixed external field is created by other components in the sensor device housing (such as speaker magnets) which have a high but static field with respect to the low (earth's) magnetic field that describes orientation information.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 5, 2016
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Lianjun Liu, Philip Mather, Jon Slaughter
  • Patent number: 9159906
    Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jon Slaughter, Nicholas Rizzo, Jijun Sun, Frederick Mancoff, Dimitri Houssameddine
  • Patent number: 9136464
    Abstract: An MRAM device, and a process for manufacturing the device, provides improved breakdown distributions, a reduced number of bits with a low breakdown voltage, and an increased MR, thereby improving reliability, manufacturability, and error-free operation. A tunnel barrier is formed between a free layer and a fixed layer in three repeating steps of forming a metal material, interceded by oxidizing each of the metal materials. The oxidization of the third metal material is greater than the dose of the first metal, but less than the dose of the second metal. The fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 15, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
  • Publication number: 20150236253
    Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine