Patents by Inventor Jon Stephan

Jon Stephan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10884853
    Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan, Vivek Kozhikkottu
  • Publication number: 20200313694
    Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K?2(K?1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Wei Wu, Vivek Kozihikkottu, Dinesh Somasekhar, Jon Stephan, Kon-Woo Kwon
  • Publication number: 20190146873
    Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Inventors: Wei Wu, Dinesh Somasekhar, Jon Stephan, Aravinda K. Radhakrishnan, Vivek Kozhikkottu