Patents by Inventor Jon T. Ewanich

Jon T. Ewanich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5159750
    Abstract: A package for containing an integrated circuit component is provided which includes one or more layers with exposed edges surrounding a central opening. The integrated circuit component is positioned in the central opening. Bond wires connect the bond pads of the integrated circuit component to the continuous shelves of the various stepped-back stadium-like layers as well as to individual insulated leads. The layers are spaced apart by beads or columns of insulative material and the major portion of the layers are separated from each other by a gaseous dielectric, preferably air. The R-C constant is reduced and the speed of transmission is increased by the presence of the low dielectric material providing a device which can function rapidly. The stepped portions of the layers are exposed to allow for electrical interconnections within the layers, as well as from each layer to the integrated circuit.
    Type: Grant
    Filed: April 3, 1991
    Date of Patent: November 3, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Vivek B. Dutta, Jeffrey C. Demmin, Mark L. Diorio, Jon T. Ewanich
  • Patent number: 5008734
    Abstract: A package for containing an integrated circuit component is provided which includes one or more layers with exposed edges surrounding a central opening. The integrated circuit component is positioned in the central opening. Bond wires connect the bond pads of the integrated circuit component to the continuous shelves of the various stepped-back stadium-like layers as well as to individual insulated leads. The layers are spaced apart by beads or columns of insulative material and the major portion of the layers are separated from each other by a gaseous dielectric, preferably air. The R-C constant is reduced and the speed of transmission is increased by the presence of the low dielectric material providing a device which can function rapidly. The stepped portions of the layers are exposed to allow for electrical interconnections within the layers, as well as from each layer to the integrated circuit.
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: April 16, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Vivek B. Dutta, Jeffrey C. Demmin, Mark L. DiOrio, Jon T. Ewanich
  • Patent number: 4833102
    Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be inspected by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: May 23, 1989
    Assignee: National Semiconductor Corporation
    Inventors: Robert C. Byrne, Jon T. Ewanich, Chee-Men Yu
  • Patent number: 4769272
    Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be insepcted by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.
    Type: Grant
    Filed: March 17, 1987
    Date of Patent: September 6, 1988
    Assignee: National Semiconductor Corporation
    Inventors: Robert C. Byrne, Jon T. Ewanich, Chee-Men Yu