Abstract: An apparatus of the present disclosure includes a controller coupled to a read/write head wherein the controller is configured to perform various operations. More specifically, the controller is configured to monitor an operational parameter of the read/write head and to detect a fault based on the operational parameter. The fault indicates that a write enabling energy source is malfunctioning during a write operation. The controller is additionally configured, in response to the fault, to take remedial action to protect data associated with the write operation.

Abstract: An apparatus of the present disclosure includes a controller coupled to a read/write head wherein the controller is configured to perform various operations. More specifically, the controller is configured to monitor an operational parameter of the read/write head and to detect a fault based on the operational parameter. The fault indicates that a write enabling energy source is malfunctioning during a write operation. The controller is additionally configured, in response to the fault, to take remedial action to protect data associated with the write operation.

Abstract: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: Apparatus for generating supply voltages in a data storage device. In some embodiments, the apparatus includes a data transducer adjacent a rotatable magnetic recording medium, the data transducer having a write coil and an electromagnetic source for thermally assisted recording by the write coil. A preamplifier/driver circuit (preamp) has a write driver adapted to supply write currents to the write coil and a source driver adapted to supply source voltage to the electromagnetic source. A voltage regulation circuit applies a first positive supply voltage to the write driver and a different, second positive supply voltage to the source driver.

Abstract: A system includes a plurality of nonvolatile memory cells and a map that assigns connections between nodes of a neural network to the memory cells. Memory devices containing nonvolatile memory cells and applicable circuitry for reading and writing may operate with the map. Information stored in the memory cells can represent weights of the connections. One or more neural processors can be present and configured to implement the neural network.

Abstract: An apparatus includes a plurality of magnetic read/write heads, a system controller and a switching network. Each of the magnetic read/write heads includes a read sensor element configured to perform a read operation and a write element configured to perform a write operation. The switching network is coupled between the plurality of magnetic read/write heads and the controller. Further, the switching network is configured to substantially simultaneously select elements from at least two of the plurality of magnetic read/write heads in response to a command from the controller such that the operations of the selected elements are performed substantially simultaneously to establish a manufacturing parameter of a disk drive.

Abstract: A data storage device receives a write data command and data. The data is stored in a buffer of the data storage device. The data storage device issues a command complete status indication. After the command complete status indication is issued, the data are stored in a primary memory of the data storage device. The primary memory comprises a first type of non-volatile memory and the buffer comprises a second type of non-volatile memory that is different from the first type of non-volatile memory.

Abstract: Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data.

Abstract: An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordance with the selected mode. A method for controlling access to the port is also provided.

Abstract: An apparatus comprises a circuit for generating a secret root key having bits representative of threshold voltages, and an error correction module for correcting errors in bits of the secret root key to produce a corrected secret root key. A method of generating a secret root key and a data storage system that includes a secret root key are also described.

Abstract: An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a non-volatile memory that can store a copy of the at least one instruction set, and a data memory that can store at least one data sequence. The data memory utilizes an error correction coding (ECC) scheme. A controller, which is responsive to the instruction memory, the non-volatile memory, and the data memory, replaces the at least one instruction set in the instruction memory with the copy of the at least one instruction set from the non-volatile memory, if a parity error is detected in connection with the at least one instruction set in the instruction memory. The controller also operates in conjunction with the data memory to implement the ECC scheme.