Abstract: Systems and methods are provided for efficient storage and/or processing of enterprise data. A set of data from a content management system (CMS) is received and interpreted to determine a hierarchical object structure for the set of data. The hierarchical object structure includes: at least one parent object; at least one child object that is a subordinate object of the parent object; an indication of each parent/child relationship; and a set of attributes for each of the objects. The set of attributes for each of the at least one parent object and the at least one child object are analyzed in light of the indication of each parent/child relationship to gather accumulated attribute data. A graphical user interface (GUI) is rendered that presents one or more graphical cards representing the objects.

Abstract: Systems and methods are provided for efficient storage and/or processing of enterprise data. A set of data from a content management system (CMS) is received and interpreted to determine a hierarchical object structure for the set of data. The hierarchical object structure includes: at least one parent object; at least one child object that is a subordinate object of the parent object; an indication of each parent/child relationship; and a set of attributes for each of the objects. The set of attributes for each of the at least one parent object and the at least one child object are analyzed in light of the indication of each parent/child relationship to gather accumulated attribute data. A graphical user interface (GUI) is rendered that presents one or more graphical cards representing the objects.

Abstract: As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

Abstract: Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. For algorithms that are highly sequential in nature, portions of algorithms can be modified to delay the need for dependent results between algorithm portions by creating a rolling window of independent tasks that is iterated.

Abstract: As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

Abstract: Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network comprises a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. To ensure consistency between the performance of algorithms, or portions thereof, in a distributed manner and a non-distributed manner, the order of processing results from execution is according to some pre-determined order, or according to the order in which the results would have been processed during a non-distributed (e.g., sequential) execution, for instance.

Abstract: Circuit test algorithms, or portions thereof, can be executed in a non-sequential manner over a network comprising a plurality of processors. Such distributed processing can improve the speed with which results are obtained and processed. Circuit testing algorithms can include, but are not limited to, test pattern generation algorithms and fault simulation algorithms. Those algorithms that are independent from each other can be executed non-sequentially (e.g., in parallel). Allocation of the various algorithm portions for execution among various processors can be based in part on a queue length associated with the processor. The queue length is adjustable based on many factors including data indicating the status of an execution maintained by the controlled processors. The faster processors can have their queue lengths increased. Multiple queue lengths can be maintained to allow for changes in allocation based on the granularity of tasks being performed by the controlling processor.

Abstract: Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner.

Abstract: Circuit test algorithms, or portions thereof, can be executed in a non-sequential manner over a network comprising a plurality of processors. Such distributed processing can improve the speed with which results are obtained and processed. Circuit testing algorithms can include, but are not limited to, test pattern generation algorithms and fault simulation algorithms. Those algorithms that are independent from each other can be executed non-sequentially (e.g., in parallel). Allocation of the various algorithm portions for execution among various processors can be based in part on a queue length associated with the processor. The queue length is adjustable based on many factors including data indicating the status of an execution maintained by the controlled processors. The faster processors can have their queue lengths increased. Multiple queue lengths can be maintained to allow for changes in allocation based on the granularity of tasks being performed by the controlling processor.

Abstract: As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be obtained by executing them in a non-distributed manner. Thus, in one aspect, the algorithms, or portions thereof, have to be made distributable. The algorithms, or portions thereof, are made distributable by isolating any random number generation therewith to be independent of each other. This isolation applies to any random number generation associated with different call instances of the same algorithm as well. In one aspect, the isolation is accomplished by ensuring that the calculation of random number sequences for the algorithms, or portions thereof, is not dependent on random number sequences calculated for the others or between call instances of the same algorithm.

Abstract: Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network comprises a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. To ensure consistency between the performance of algorithms, or portions thereof, in a distributed manner and a non-distributed manner, the order of processing results from execution is according to some pre-determined order, or according to the order in which the results would have been processed during a non-distributed (e.g., sequential) execution, for instance.

Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.