Patents by Inventor Jonah Alben

Jonah Alben has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220114069
    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Jonah ALBEN, Sachin Idgunji, Jue Wu, Shantanu Sarangi
  • Patent number: 11204849
    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: December 21, 2021
    Assignee: NVIDIA Corporation
    Inventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
  • Publication number: 20210286693
    Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Jonah ALBEN, Sachin Idgunji, Jue Wu, Shantanu Sarangi
  • Publication number: 20210191754
    Abstract: Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Jonathon Evans, Lacky Shah, Phil Johnson, Jonah Alben, Brian Pharris, Greg Palmer, Brian Fahs
  • Patent number: 10430989
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 1, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Cynthia Allison, Dale Kirkland, Jeffrey Bolz, Yury Uralsky, Jonah Alben
  • Patent number: 10147222
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 4, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Cynthia Allison, Dale Kirkland, Jeffrey Bolz, Yury Uralsky, Jonah Alben
  • Publication number: 20180322391
    Abstract: In training a deep neural network using reduced precision, gradient computation operates on larger values without affecting the rest of the training procedure. One technique trains the deep neural network to develop loss, scales the loss, computes gradients at a reduced precision, and reduces the magnitude of the computed gradients to compensate for scaling of the loss. In one example non-limiting arrangement, the training forward pass scales a loss value by some factor S and the weight update reduces the weight gradient contribution by 1/S. Several techniques can be used for selecting scaling factor S and adjusting the weight update.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 8, 2018
    Inventors: Hao WU, Jonah ALBEN, Paulius MICIKEVICIUS
  • Patent number: 9829967
    Abstract: A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: November 28, 2017
    Assignee: NVIDIA Corporation
    Inventors: Sam Duell, Jonah Alben, Andrew R. Bell, Ming Chen, Gabriele Gorla, Qi Lin, Henry Pang, Gokul Santhirakumaran
  • Publication number: 20170148203
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Ziyad HAKURA, Cynthia ALLISON, Dale KIRKLAND, Jeffrey BOLZ, Yury URALSKY, Jonah ALBEN
  • Publication number: 20170148204
    Abstract: A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Ziyad HAKURA, Cynthia ALLISON, Dale KIRKLAND, Jeffrey BOLZ, Yury URALSKY, Jonah ALBEN
  • Publication number: 20170102760
    Abstract: A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.
    Type: Application
    Filed: October 8, 2015
    Publication date: April 13, 2017
    Inventors: Sam DUELL, Jonah ALBEN, Andrew R. BELL, Ming CHEN, Gabriele Gorla, Qi LIN, Henry PANG, Gokul SANTHIRAKUMARAN
  • Patent number: 8890573
    Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 18, 2014
    Assignee: Nvidia Corporation
    Inventors: Ilyas Elkin, Ge Yang, Jonah Alben
  • Patent number: 8742796
    Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 3, 2014
    Assignee: Nvidia Corporation
    Inventors: William Dally, Jonah Alben
  • Publication number: 20140070847
    Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: Nvidia Corporation
    Inventors: Ilyas Elkin, Ge Yang, Jonah Alben
  • Publication number: 20120182056
    Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 19, 2012
    Applicant: NVIDIA CORPORATION
    Inventors: William Dally, Jonah Alben
  • Publication number: 20070139426
    Abstract: A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 21, 2007
    Inventors: Joseph Greco, Jonah Alben, Barry Wagner, Anthony Tamasi
  • Publication number: 20060132491
    Abstract: In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.
    Type: Application
    Filed: December 20, 2004
    Publication date: June 22, 2006
    Applicant: NVIDIA Corporation
    Inventors: Duncan Riach, John Danskin, Jonah Alben, Michael Ogrinc, Anthony Tamasi
  • Publication number: 20060028478
    Abstract: A computer system includes an integrated graphics subsystem and a graphics connector for attaching either an auxiliary graphics subsystem or a loopback card. A first bus connection communicates data from the computer system to the integrated graphics subsystem. With a loopback card in place, data travels from the integrated graphics subsystem back to the computer system via a second bus connection. When the auxiliary graphics subsystem is attached, the integrated graphics subsystem operates in a data forwarding mode. Data is communicated to the integrated graphics subsystem via the first bus connection. The integrated graphics subsystem then forwards data to the auxiliary graphics subsystem. A portion of the second bus connection communicates data from the auxiliary graphics subsystem back to the computer system. The auxiliary graphics subsystem communicates display information back to the integrated graphics subsystem, where it is used to control a display device.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 9, 2006
    Applicant: NVIDIA CORPORATION
    Inventors: Oren Rubinstein, Jonah Alben, Wei-Je Huang
  • Publication number: 20050268141
    Abstract: A graphics processing device implementing a set of techniques for power management, preferably at both a subsystem level and a device level, and preferably including peak: power management, a system including a graphics processing device that implements such a set of techniques for power management, and the power management methods performed by such a device or system. In preferred embodiments, the device includes at least two subsystems and hardware mechanisms that automatically seek the lowest power state for the device that does not impact performance of the device or of a system that includes the device. Preferably, the device includes a control unit operable in any selected one of multiple power management modes, and system software can intervene to cause the control unit to operate in any of these modes. For example, the device can include a register interface to which an external processor can write control bits to select among the modes.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 1, 2005
    Inventors: Jonah Alben, Dennis Ma, Brian Kelleher
  • Publication number: 20050237327
    Abstract: A computer system includes an integrated graphics subsystem and a graphics connector for attaching either an auxiliary graphics subsystem or a loopback card. A first bus connection communicates data from the computer system to the integrated graphics subsystem. With a loopback card in place, data travels from the integrated graphics subsystem back to the computer system via a second bus connection. When the auxiliary graphics subsystem is attached, the integrated graphics subsystem operates in a data forwarding mode. Data is communicated to the integrated graphics subsystem via the first bus connection. The integrated graphics subsystem then forwards data to the auxiliary graphics subsystem. A portion of the second bus connection communicates data from the auxiliary graphics subsystem back to the computer system. The auxiliary graphics subsystem communicates display information back to the integrated graphics subsystem, where it is used to control a display device.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 27, 2005
    Applicant: NVIDIA Corporation
    Inventors: Oren Rubinstein, Jonah Alben, Wei-Je Huang