Abstract: Methods and apparatus are provided for accessing the proper memory in processors having program and data memories with different sizes. In some embodiments, a processor is optimized for data access and has registers that are the same size as the data memories. When a program is compiled, some implementations identify when a pointer variable points to a piece of data (data memory) or a function (program memory) and synthesize different sized operations accordingly. The proper mode and size are assigned for each pointer. Methods of the present invention do not require annotation of functions. Existing code does not need to be modified and there is no opportunity to introduce errors. The invention does not require extra program memory to be located at directly accessible locations to store stub code.

Abstract: A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.

Abstract: A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.