Patents by Inventor Jonah M. Alben

Jonah M. Alben has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10338919
    Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 2, 2019
    Assignee: NVIDIA Corporation
    Inventors: Brent Ralph Boswell, Ming Y. Siu, Jack H. Choquette, Jonah M. Alben, Stuart Oberman
  • Publication number: 20190139269
    Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.
    Type: Application
    Filed: December 4, 2018
    Publication date: May 9, 2019
    Inventors: Yury Y. URALSKY, Jonah M. ALBEN, Ankan BANERJEE, Gregory MASSAL, Thomas PETERSEN, Oleg KUZNETSOV, Eric B. LUM, Prakshep MEHTA
  • Patent number: 10147203
    Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: December 4, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Yury Y. Uralsky, Jonah M. Alben, Ankan Banerjee, Gregory Massal, Thomas Petersen, Oleg Kuznetsov, Eric B. Lum, Prakshep Mehta
  • Publication number: 20180321938
    Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.
    Type: Application
    Filed: November 29, 2017
    Publication date: November 8, 2018
    Inventors: Brent Ralph Boswell, Ming Y. Siu, Jack H. Choquette, Jonah M. Alben, Stuart Oberman
  • Patent number: 10102668
    Abstract: A system, method, and computer program product are provided for rendering at variable sampling rates. Vertex coordinates for 3D primitive are received from a shader execution unit, and an arithmetic operation is performed on the vertex coordinates by fixed operation circuitry to produce modified vertex coordinates in homogeneous coordinate space. The modified vertex coordinates are transformed from homogeneous coordinate space into screen-space to produce screen-space vertex coordinates of a transformed 3D primitive and the transformed 3D primitive is rasterized in screen-space using the screen-space vertex coordinates to produce an image for display.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 16, 2018
    Assignee: NVIDIA Corporation
    Inventors: Henry Packard Moreton, Jonah M. Alben
  • Patent number: 10096086
    Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: October 9, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Yury Y. Uralsky, Jonah M. Alben, Ankan Banerjee, Gregory Massal, Thomas Petersen, Oleg Kuznetsov, Eric B. Lum, Prakshep Mehta
  • Publication number: 20170323475
    Abstract: A system, method, and computer program product are provided for rendering at variable sampling rates. Vertex coordinates for 3D primitive are received from a shader execution unit, and an arithmetic operation is performed on the vertex coordinates by fixed operation circuitry to produce modified vertex coordinates in homogeneous coordinate space. The modified vertex coordinates are transformed from homogeneous coordinate space into screen-space to produce screen-space vertex coordinates of a transformed 3D primitive and the transformed 3D primitive is rasterized in screen-space using the screen-space vertex coordinates to produce an image for display.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 9, 2017
    Inventors: Henry Packard Moreton, Jonah M. Alben
  • Publication number: 20160071246
    Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.
    Type: Application
    Filed: September 5, 2015
    Publication date: March 10, 2016
    Inventors: Yury Y. URALSKY, Jonah M. ALBEN, Ankan BANJEREE, Gregory MASSAL, Thomas PETERSON, Oleg KUZNETSOV, Eric B. LUM, Prakshep MEHTA
  • Publication number: 20160071242
    Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.
    Type: Application
    Filed: September 5, 2015
    Publication date: March 10, 2016
    Inventors: Yury Y. URALSKY, Jonah M. ALBEN, Ankan BANJEREE, Gregory MASSAL, Thomas PETERSON, Oleg KUZNETSOV, Eric B. LUM, Prakshep MEHTA
  • Patent number: 9170980
    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Thomas Hastings Greer, III
  • Patent number: 9164766
    Abstract: Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 20, 2015
    Assignee: NVIDIA Corporation
    Inventors: Aron L. Wong, Dennis K. Ma, Jonah M. Alben, Mark S. Krueger, Jeffrey J. Irwin
  • Patent number: 9153539
    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: October 6, 2015
    Assignee: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Thomas Hastings Greer, III
  • Patent number: 9077329
    Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: July 7, 2015
    Assignee: NVIDIA Corporation
    Inventors: Ilyas Elkin, William J. Dally, Jonah M. Alben
  • Publication number: 20140281383
    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-, ended signaling interface advantageously implements ground-referenced single-ended signaling.
    Type: Application
    Filed: August 22, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Thomas Hastings Greer, III
  • Publication number: 20140266417
    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.
    Type: Application
    Filed: August 22, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA Corporation
    Inventors: William J. Dally, Jonah M. Alben, John W. Poulton, Thomas Hastings Greer, III
  • Patent number: 8786345
    Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: July 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, William J. Dally
  • Patent number: 8782349
    Abstract: Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: Brian Keith Langendorf, David B. Glasco, Michael Brian Cox, Jonah M. Alben
  • Publication number: 20140125393
    Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: NVIDIA Corporation
    Inventors: Ilyas Elkin, William J. Dally, Jonah M. Alben
  • Patent number: 8707081
    Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: April 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, Sean Jeffrey Treichler, Adam E. Levinthal
  • Patent number: 8659337
    Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: February 25, 2014
    Assignee: NVIDIA Corporation
    Inventors: Ilyas Elkin, William James Dally, Jonah M. Alben