Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.

Abstract: The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed.

Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.

Abstract: Memory transactions that are issued just in time have deterministic response delay. By measuring an actual delay and comparing it to an expected delay a memory scheduler can determine whether it is issuing transaction requests too early and can thereby automatically adapt the issue of transaction requests by delaying future transaction requests to be just in time.

Abstract: A processor system includes a plurality of processors, along with a target device, e.g., a memory, having two or more ports, and an arbiter that arbitrates access requests from requesting processors. A multiplexer facilitates the flow of control, address and data information over a shared bus. The number of processors requesting access may be greater than the number of target ports. Each processor can issue a request for access to communicate with a target port at any time by a transaction, such as a data read or write. The arbiter may simultaneously grant access to as many requesting processors up to the number of target ports. The arbiter dynamically and arbitrarily allocates each target port to a requesting processor at the time of the request for access, which may occur within each system clock cycle, and each access may last for one or more clock cycles. The data transfer for each processor granted access may be transmitted through the target port and through the multiplexer.

Abstract: A processor, e.g., a VLIW processor, may include two separate execution units, a first execution unit may have a general-purpose register file and an arithmetic logic unit. The register file may source operands to the ALU, and the result of the ALU operation may be stored in the register file or an accumulator. A second execution unit may include instruction control logic that executes an instruction which causes data to be moved through a data path within the first execution unit, e.g., from the ALU or accumulator to the register file, or to and/or from the execution unit. Thus, for example, the first execution unit performs a multiplication operation while the second execution unit moves the results of a multiplication operation (e.g., the most recent multiplication operation) to the register file.