Patents by Inventor Jonas Goode
Jonas Goode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12580017Abstract: Example channel circuits, data storage devices, and methods for using a trained neural network to estimate the noise mixture in a read signal are described. Samples are determined from a digital read signal, such as the read signal from the non-volatile storage medium of a data storage device. The samples are processed through one or more instances of a neural network comprised of trained coefficients and outputting a set of estimate values for a noise mixture of the read signal. The set of estimate values may then be used to adjust parameters of the read channel for processing the read signal to detect and decode data.Type: GrantFiled: July 18, 2023Date of Patent: March 17, 2026Assignee: Western Digital Technologies, Inc.Inventors: Minghai Qin, Chao Sun, Dejan Vucinic, Henry Yip, Jonas Goode, Richard Galbraith, Iouri Oboukhov
-
Patent number: 12474994Abstract: Example systems and methods for using synchronization marks to correct insertions and deletions for DNA data storage are described. A data unit may be encoded in oligos that include synchronization marks at predetermined intervals along the length of each oligo. During decoding, the synchronization marks may improve identification and isolation of insertions and deletions for correction of symbol alignment prior to error correction code decoding. In some configurations, correlation analysis may be used to improve isolation of insertions and deletions where multiple copies of the same oligo are available.Type: GrantFiled: November 1, 2023Date of Patent: November 18, 2025Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard Galbraith, Niranjay Ravindran, Jonas Goode, Weldon M. Hanson
-
Patent number: 12430202Abstract: Example systems and methods for using nested error correction codes for DNA data storage are described. A data unit may be encoded in a set of oligos. Using an error correction code, such as an LDPC code, a codeword may be determined for the data unit that is a multiple of the data payload capacity of each oligo. The codeword may be divided among the set of oligos, along with corresponding redundancy data. Any number of additional levels of nested error correction codes may be implemented by aggregating sets of smaller codewords into larger codewords and storing the corresponding redundancy data in the set of oligos. Each nested level may be aggregated from the set of oligos and decoded using the corresponding error correction code matrix and set of redundancy data as needed, such as in response to failure to decode codewords at a lower level.Type: GrantFiled: November 1, 2023Date of Patent: September 30, 2025Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard Galbraith, Niranjay Ravindran, Jonas Goode, Weldon M. Hanson
-
Patent number: 12399778Abstract: Example channel circuits, data storage devices, and methods for using zero force adaptation to equalize a read data signal based on known data are described. A known user data signal may be determined during prior read operations and used with a residue term from the equalized read data signal to adapt the tap weights for an equalizer filter using a zero force adaptation algorithm. For example, the known user data signal may be determined by a soft output detector (e.g., SOVA detector) or full or partial decoding by an iterative decoder (e.g., LDPC decoder) and fed back for adapting the equalizer.Type: GrantFiled: December 7, 2023Date of Patent: August 26, 2025Assignee: Western Digital Technologies, Inc.Inventors: Richard Galbraith, Pradhan Bellam, Iouri Oboukhov, Niranjay Ravindran, Weldon Hanson, Jonas Goode
-
Patent number: 12374365Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.Type: GrantFiled: December 6, 2023Date of Patent: July 29, 2025Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
-
Patent number: 12373130Abstract: Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.Type: GrantFiled: July 19, 2023Date of Patent: July 29, 2025Assignee: Western Digital Technologies, Inc.Inventors: Richard Galbraith, Iouri Oboukhov, Jonas Goode, Niranjay Ravindran, Pradhan Bellam, Henry Yip
-
Publication number: 20250190307Abstract: Example channel circuits, data storage devices, and methods for using zero force adaptation to equalize a read data signal based on known data are described. A known user data signal may be determined during prior read operations and used with a residue term from the equalized read data signal to adapt the tap weights for an equalizer filter using a zero force adaptation algorithm. For example, the known user data signal may be determined by a soft output detector (e.g., SOVA detector) or full or partial decoding by an iterative decoder (e.g., LDPC decoder) and fed back for adapting the equalizer.Type: ApplicationFiled: December 7, 2023Publication date: June 12, 2025Inventors: Richard Galbraith, Pradhan Bellam, Iouri Oboukhov, Niranjay Ravindran, Weldon Hanson, Jonas Goode
-
Patent number: 12315534Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using symbol context mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. The configuration settings may be determined by determining a known pattern for a sector, determining a series of symbol contexts, determining mutual information for each symbol context, and using the symbol context mutual information to determine relationships among configuration settings, such as bit size, error correction code rate, and modulation code. Once determined, the configuration settings may be used to configure the modulation code and ECC rate for the channel circuit of the data storage device.Type: GrantFiled: December 6, 2023Date of Patent: May 27, 2025Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
-
Patent number: 12183376Abstract: Example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. A data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. The write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.Type: GrantFiled: August 3, 2023Date of Patent: December 31, 2024Assignee: Western Digital Technologies, Inc.Inventors: Richard Galbraith, Jonas Goode, Niranjay Ravindran, Iouri Oboukhov
-
Publication number: 20240420735Abstract: Example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. A data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. The write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.Type: ApplicationFiled: August 3, 2023Publication date: December 19, 2024Inventors: Richard Galbraith, Jonas Goode, Niranjay Ravindran, Iouri Oboukhov
-
Publication number: 20240264765Abstract: Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.Type: ApplicationFiled: July 19, 2023Publication date: August 8, 2024Inventors: Richard Galbraith, Iouri Oboukhov, Jonas Goode, Niranjay Ravindran, Pradhan Bellam, Henry Yip
-
Publication number: 20240265943Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.Type: ApplicationFiled: December 6, 2023Publication date: August 8, 2024Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
-
Publication number: 20240265948Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using symbol context mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. The configuration settings may be determined by determining a known pattern for a sector, determining a series of symbol contexts, determining mutual information for each symbol context, and using the symbol context mutual information to determine relationships among configuration settings, such as bit size, error correction code rate, and modulation code. Once determined, the configuration settings may be used to configure the modulation code and ECC rate for the channel circuit of the data storage device.Type: ApplicationFiled: December 6, 2023Publication date: August 8, 2024Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
-
Patent number: 12028091Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.Type: GrantFiled: September 26, 2022Date of Patent: July 2, 2024Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Derrick E. Burton, Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Jonas Goode
-
Publication number: 20240211729Abstract: Example systems, read channels, and methods provide multiple neural network training nodes for processing read data signals prior to symbol detection and decoding. A plurality of neural network circuits receive read data signals and modify them based on different neural network configurations and sets of trained node coefficients. Each neural network circuit may pass modified read data signals directly to another neural network circuit or determine a parameter for modifying processing of the read data signals by another component. In some configurations, the last neural network circuit may pass the output read data signal to a soft output detector for determining the symbols in the read data signal.Type: ApplicationFiled: July 19, 2023Publication date: June 27, 2024Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Henry Yip, Niranjay Ravindran
-
Publication number: 20240184666Abstract: Example systems and methods for using synchronization marks to correct insertions and deletions for DNA data storage are described. A data unit may be encoded in oligos that include synchronization marks at predetermined intervals along the length of each oligo. During decoding, the synchronization marks may improve identification and isolation of insertions and deletions for correction of symbol alignment prior to error correction code decoding. In some configurations, correlation analysis may be used to improve isolation of insertions and deletions where multiple copies of the same oligo are available.Type: ApplicationFiled: November 1, 2023Publication date: June 6, 2024Inventors: Iouri Oboukhov, Richard Galbraith, Niranjay Ravindran, Jonas Goode, Weldon M. Hanson
-
Publication number: 20240185959Abstract: Example systems and methods for using nested error correction codes for DNA data storage are described. A data unit may be encoded in a set of oligos. Using an error correction code, such as an LDPC code, a codeword may be determined for the data unit that is a multiple of the data payload capacity of each oligo. The codeword may be divided among the set of oligos, along with corresponding redundancy data. Any number of additional levels of nested error correction codes may be implemented by aggregating sets of smaller codewords into larger codewords and storing the corresponding redundancy data in the set of oligos. Each nested level may be aggregated from the set of oligos and decoded using the corresponding error correction code matrix and set of redundancy data as needed, such as in response to failure to decode codewords at a lower level.Type: ApplicationFiled: November 1, 2023Publication date: June 6, 2024Inventors: Iouri Oboukhov, Richard Galbraith, Niranjay Ravindran, Jonas Goode, Weldon M. Hanson
-
Publication number: 20240170056Abstract: Example channel circuits, data storage devices, and methods for using a trained neural network to estimate the noise mixture in a read signal are described. Samples are determined from a digital read signal, such as the read signal from the non-volatile storage medium of a data storage device. The samples are processed through one or more instances of a neural network comprised of trained coefficients and outputting a set of estimate values for a noise mixture of the read signal. The set of estimate values may then be used to adjust parameters of the read channel for processing the read signal to detect and decode data.Type: ApplicationFiled: July 18, 2023Publication date: May 23, 2024Inventors: Minghai Qin, Chao Sun, Dejan Vucinic, Henry Yip, Jonas Goode, Richard Galbraith, Iouri Oboukhov
-
Patent number: 11978524Abstract: A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.Type: GrantFiled: August 25, 2021Date of Patent: May 7, 2024Assignee: Western Digital Technologies, Inc.Inventors: Jonas Goode, Richard Galbraith, Henry Yip, Vinh Hoang
-
Patent number: 11953987Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.Type: GrantFiled: September 16, 2022Date of Patent: April 9, 2024Assignee: Western Digital Technologies, Inc.Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Henry Yip, Niranjay Ravindran