Patents by Inventor Jonas H. Kapraun

Jonas H. Kapraun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11881683
    Abstract: A semiconductor device fabrication method in which a growing process is followed by a capping process in which a phosphor containing material cap layer is deposited over a final GaAs based layer. The wafer, containing many such substrates, can be removed from the reaction chamber to continue processing at a later time without creating an oxide layer on the final GaAs based layer. In continuing processing, a decomposition process selectively decomposes the phosphor containing material cap layer, after which a regrowing process is performed to grow additional layers of the device structure. The capping, decomposition and regrowth processes can be repeated multiple times on the semiconductor devices on the wafer during device fabrication.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: January 23, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Constance J. Chang-Hasnain, Jiaxing Wang, Jonas H. Kapraun, Emil Kolev
  • Publication number: 20210159668
    Abstract: A vertical cavity surface emitter device (e.g., VCSEL or RC-LED) containing a buried index-guiding current confinement aperture layer which is grown, and lithographically processed to define position, shape and dimension of an inner aperture. In a regrowth process, the aperture is filled with a single crystalline material from the third contact layer. The aperture provides for both current and optical confinement, while allowing for higher optical power output and improved thermal conductivity.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 27, 2021
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Constance J. Chang-Hasnain, Jiaxing Wang, Kevin T. Cook, Jonas H. Kapraun, Emil Kolev
  • Publication number: 20210159669
    Abstract: A semiconductor device fabrication method in which a growing process is followed by a capping process in which a phosphor containing material cap layer is deposited over a final GaAs based layer. The wafer, containing many such substrates, can be removed from the reaction chamber to continue processing at a later time without creating an oxide layer on the final GaAs based layer. In continuing processing, a decomposition process selectively decomposes the phosphor containing material cap layer, after which a regrowing process is performed to grow additional layers of the device structure. The capping, decomposition and regrowth processes can be repeated multiple times on the semiconductor devices on the wafer during device fabrication.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 27, 2021
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Constance J. Chang-Hasnain, Jiaxing Wang, Jonas H. Kapraun, Emil Kolev