Patents by Inventor Jonas Hoehenberger

Jonas Hoehenberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11869725
    Abstract: A stacked capacitor includes a capacitor stack. The capacitor stack includes a base plate having a first surface and a second opposing surface, a first dielectric layer on or over the base plate, and a first conductive plate on or over the first dielectric layer. A second dielectric layer is on or over the first conductive plate. A second conductive plate on or over the second dielectric layer. The capacitor stack has at least one sloped side with at least one slope with respect to the second surface of the base plate.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 9, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Hans Enzelberger-Heim, Jonas Höhenberger
  • Publication number: 20230366832
    Abstract: A wafer metrology system including a dynamic sampling scheme configured to optimize a sampling rate for measurement of process wafers in an IC fabrication flow based on process capability index data as well as measurement history data. For a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.
    Type: Application
    Filed: September 29, 2022
    Publication date: November 16, 2023
    Inventors: Jonas Hoehenberger, Moritz Steinberg, Pietro Foglietti, Alexander Sirch
  • Publication number: 20230170314
    Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: June 1, 2023
    Inventors: Jonas Höhenberger, Gernot Biese
  • Publication number: 20230170153
    Abstract: A stacked capacitor includes a capacitor stack. The capacitor stack includes a base plate having a first surface and a second opposing surface, a first dielectric layer on or over the base plate, and a first conductive plate on or over the first dielectric layer. A second dielectric layer is on or over the first conductive plate. A second conductive plate on or over the second dielectric layer. The capacitor stack has at least one sloped side with at least one slope with respect to the second surface of the base plate.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Michael Hans ENZELBERGER-HEIM, Jonas HÖHENBERGER
  • Patent number: 11587889
    Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Jonas Höhenberger, Gernot Biese
  • Publication number: 20220179096
    Abstract: This disclosure relates to wind detection and vehicle control. In an example, sensor data can be generated by one or more wind sensing devices for a vehicle that includes at least one light detection and ranging (LIDAR) device. The sensor data can characterize a movement of airborne particles. Wind characteristics can be determined based on the sensor data. A vehicle operating parameter can be updated based on the determined wind characteristics.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventor: Jonas Hoehenberger
  • Publication number: 20210091013
    Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 25, 2021
    Inventors: Jonas Höhenberger, Gernot Biese