Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0: m]mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of [log2 M]; and more than M?2u of the subset of modulo units are arranged at the maximal delay of [log2 M], where 2u is the power of 2 immediately smaller than M.

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b > a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M - 1 modulo units of the logarithmic tree provide x[0: m]mod d for all m ? {1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of log2 M; and more than M - 2u of the subset of modulo units are arranged at the maximal delay of log2 M, where 2u is the power of 2 immediately smaller than M.

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0:m]mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log 2M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log 2M?, where 2u is the power of 2 immediately smaller than M.

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0: m] mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log2 M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log2 M?, where 2u is the power of 2 immediately smaller than M.

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0:m]mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log2 M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log2 M?, where 2u is the power of 2 immediately smaller than M.

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b] mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M?1 modulo units of the logarithmic tree provide x[0: m] mod d for all m?{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ?log2 M?; and more than M?2u of the subset of modulo units are arranged at the maximal delay of ?log2 M?, where 2u is the power of 2 immediately smaller than M.