Patents by Inventor Jonathan A. Dama
Jonathan A. Dama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11700209Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.Type: GrantFiled: December 26, 2019Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Robert Southworth, Karl S. Papadantonakis, Mika Nystroem, Arvind Srinivasan, David Arditti Ilitzky, Jonathan Dama
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Patent number: 11641326Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.Type: GrantFiled: August 23, 2019Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Karl S. Papadantonakis, Robert Southworth, Arvind Srinivasan, Helia A. Naeimi, James E. McCormick, Jr., Jonathan Dama, Ramakrishna Huggahalli, Roberto Penaranda Cebrian
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Publication number: 20200412649Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20200412666Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.Type: ApplicationFiled: August 23, 2019Publication date: December 31, 2020Inventors: Karl S. PAPADANTONAKIS, Robert SOUTHWORTH, Arvind SRINIVASAN, Helia A. NAEIMI, James E. McCORMICK, JR., Jonathan DAMA, Ramakrishna HUGGAHALLI, Roberto PENARANDA CEBRIAN
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Patent number: 10785150Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.Type: GrantFiled: September 25, 2015Date of Patent: September 22, 2020Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20200159654Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Inventors: Sanjeev Jain, Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20200136986Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.Type: ApplicationFiled: December 26, 2019Publication date: April 30, 2020Inventors: Robert SOUTHWORTH, Karl S. PAPADANTONAKIS, Mika NYSTROEM, Arvind SRINIVASAN, David ARDITTI ILITZKY, Jonathan DAMA
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Patent number: 10621080Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.Type: GrantFiled: April 1, 2016Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Sanjeev Jain, Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Patent number: 9992125Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: GrantFiled: August 16, 2016Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Publication number: 20170286006Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Sanjeev Jain, Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20170093709Abstract: A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20170093708Abstract: A communication packet processing device may include a control stage coupled to receive multiple headers of a packet comprised of multiple words, and to determine a destination lane for each word of the multiple headers by counting previous words of the headers. The device may also include a level 1 permutation circuit coupled to the control stage to place each word into a correct lane responsive to the determined destination lane, and a level 2 permutation circuit coupled to the level 1 permutation t circuit o place each word into a correct designation lane responsive to the determined destination lane. Additional embodiments are also described.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Karl S. Papadantonakis, Robert G. Southworth, Alain Gravel, Jonathan A. Dama
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Publication number: 20160359754Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Inventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Patent number: 9426096Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: GrantFiled: May 21, 2014Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Publication number: 20150341277Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Inventors: Alain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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Patent number: 8370557Abstract: A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.Type: GrantFiled: December 19, 2008Date of Patent: February 5, 2013Assignee: Intel CorporationInventors: Jonathan Dama, Andrew Lines
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Publication number: 20100161892Abstract: A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.Type: ApplicationFiled: December 19, 2008Publication date: June 24, 2010Applicant: FULCRUM MICROSYSTEMS, INC.Inventors: Jonathan Dama, Andrew Lines
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Patent number: 7301362Abstract: Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.Type: GrantFiled: March 14, 2006Date of Patent: November 27, 2007Assignee: California Institute of TechnologyInventors: Wonjin Jang, Alain J. Martin, Mika Nystroem, Jonathan A. Dama
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Publication number: 20070016823Abstract: Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.Type: ApplicationFiled: March 14, 2006Publication date: January 18, 2007Applicant: California Institute of TechnologyInventors: Wonjin Jang, Alain Martin, Mika Nystroem, Jonathan Dama