Abstract: A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals.