Abstract: A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

Abstract: A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

Abstract: The present invention provides a window structure which is easily constructed and less expensive to produce than prior art window structures. The window structure includes a metallic sash having an L-shaped cross section which retains an insulated window lite containing a plurality of panes of glass. Glazing tape is placed on the portions of the L-shaped sash which are in plane with the panes of glass and the window lite is seated on one or more setting blocks located on the weight bearing structure of the sash. The window lite is securely mounted to the sash with a silicone adhesive which bonds the edges of the panes of glass to the sash. The silicone adhesive also acts as a thermal break to reduce heat transfer between exterior and interior sides of the window structure. The window structure of the present invention is elegantly simple in comparison to prior art structures since it takes advantage of the inherent rigidity of insulating window lite structures.

Abstract: An integrated circuit test wafer quickly detects A-C defects in any process by which the wafer is fabricated. This test wafer includes a semiconductor substrate having a major surface, and a diagnostic circuit that is repeatedly integrated over most of the wafer's surface. Each diagnostic circuit includes: a) a plurality of ring oscillators which generate respective cyclic output signals; b) an addressing circuit that receives external input signals and in response selects an output signal from any particular ring oscillator of the plurality; c) a timing circuit that generates a timing signal with a certain time period; and, d) a counting circuit that counts the number of cycles that occur in the selected output signal during the time period and provides that number as an output.

Abstract: An improved standard cell logic chip, of the type which contains one to fifteen thousand standard logic cells that are disposed in rows on a substrate, and has cell interconnect channels of different widths between the rows, also includes fast change logic cells which are sparsely distributed in the rows of standard logic cells. Each fast change cell selectively performs any one of several logic functions. These fast change logic cells are formed from the same stacked conductive and insulative layers as the standard logic cells; however, in the fast change cells, all conductive and insulative layers which are below at least the mid level in the stack of layers have respective patterns which are identical in every fast change cell. Only the remaining conductive and insulative layers in the fast change cells have respective patterns which differ from one fast change cell to another, and they select the logical functions which the fast change cells perform.