Patents by Inventor Jonathan A. White

Jonathan A. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SUPER-RESOLVED OBJECT DETECTION WITH SPATIAL GENOMICS
    Publication number: 20250284910
    Abstract: The present disclosure provides methods for encoding and decoding signals from barcodes in a plurality of molecular targets from images obtained from imaging based spatial genomics (ISG) experiments. This disclosure sets forth methods, in addition to use of the same, and other solutions to problems in the relevant field.
    Type: Application
    Filed: February 12, 2025
    Publication date: September 11, 2025
    Inventors: Jonathan A. WHITE, Long CAI
  • Analyzing Test Case Failures
    Publication number: 20080222501
    Abstract: Apparatus and method for categorizing test failures are disclosed. In one embodiment, a data set of a current test failure is compared with the data sets of historical test failures to result in a set of correspondence values. The current test failure is categorized with respect to the historical test failures at least in part on the basis of the correspondence values.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 11, 2008
    Applicant: Microsoft Corporation
    Inventors: Daniel T. Travison, Jonathan A. White, John A. Messec
  • Virtual ground circuit
    Patent number: 6794902
    Abstract: Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: September 21, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Matthew E. Becker, Harry R. Fair, III, Marc E. Lamere, Jonathan A. White
  • Virtual Ground Circuit
    Publication number: 20030231030
    Abstract: Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 18, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Matthew E. Becker, Harry R. Fair, Marc E. Lamere, Jonathan A. White