Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Abstract: Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Abstract: The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Abstract: Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Abstract: The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Abstract: The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Abstract: The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Abstract: An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).

Abstract: An architecture for microprocessors, in which instructions include a type identifier, selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).

Abstract: Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Abstract: The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag.

Abstract: Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.

Abstract: An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).