Abstract: A data processing device is disclosed, which comprises a plurality of data processing hardware components, such as one or more of a microprocessor, a central processing unit, a system on chip hardware component, a conditional access hardware component, a descrambler hardware component, a graphics hardware component, a video hardware component and a field programmable gate array hardware component. A first hardware component of the plurality of data processing hardware components is configured to send a challenge to at least one remaining hardware component of the plurality of data processing hardware components. Each remaining hardware component is configured to receive a respective challenge and to process the challenge to produce one or more respective responses. The device is configured to use one or more responses to verify device integrity.