Patents by Inventor Jonathan Bornstein

Jonathan Bornstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200274156
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Inventors: Weijie Wang, Zuqin Liu, Song Han, Jonathan Bornstein, Constantin Ionel Stefan
  • Publication number: 20200274151
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon-based coating is provided. The silicon coating may include a non-conformal, more porous silicon-rich SiEx layer and a conformal, denser SiEx layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes are used: a PECVD layer to deposit the non-conformal, silicon-rich SiEx layer and a thermal CVD process to deposit the conformal layer. The silicon-rich SiEx material prevents silicon crystalline domain growth, limits macroscopic swelling, increases lithium diffusion rate and enhances significantly battery life during lithium ion battery cycle of charge and discharge.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 27, 2020
    Inventors: Chentao Yu, Weijie Wang, Constantin Ionel Stefan, Jonathan Bornstein, Daniel Seo
  • Patent number: 10707484
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 7, 2020
    Assignee: Amprius, Inc.
    Inventors: Weijie Wang, Zuqin Liu, Song Han, Jonathan Bornstein, Constantin Ionel Stefan
  • Publication number: 20190088939
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.
    Type: Application
    Filed: February 2, 2018
    Publication date: March 21, 2019
    Inventors: Weijie Wang, Zuqin Liu, Song Han, Jonathan Bornstein, Constantin Ionel Stefan
  • Patent number: 9923201
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: March 20, 2018
    Assignee: Amprius, Inc.
    Inventors: Weijie Wang, Zuqin Liu, Song Han, Jonathan Bornstein, Constantin Ionel Stefan
  • Publication number: 20150325852
    Abstract: Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.
    Type: Application
    Filed: May 12, 2015
    Publication date: November 12, 2015
    Inventors: Weijie Wang, Zuqin Liu, Song Han, Jonathan Bornstein, Constantin Ionel Stefan
  • Patent number: 8390100
    Abstract: Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: March 5, 2013
    Assignee: Unity Semiconductor Corporation
    Inventor: Jonathan Bornstein
  • Patent number: 8268667
    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: September 18, 2012
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Robin Cheung, David Hansen, Steven Longcor, Rene Meyer, Jonathan Bornstein, Lawrence Schloss
  • Patent number: 8237142
    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 7, 2012
    Assignee: Unity Semiconductor Corporation
    Inventors: Robin Cheung, Jonathan Bornstein, David Hansen, Travis Byonghyop Oh, Darrell Rinerson
  • Publication number: 20110315943
    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the un-etched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, JONATHAN BORNSTEIN, DAVID HANSEN, ROBIN CHEUNG, STEVEN W. LONGCOR, RENE MEYER, LAWRENCE SCHLOSS
  • Publication number: 20110315948
    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
    Type: Application
    Filed: August 23, 2011
    Publication date: December 29, 2011
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, JONATHAN BORNSTEIN, DAVID HANSEN, ROBIN CHEUNG, STEVEN W. LONGCOR, RENE MEYER, LAWRENCE SCHLOSS
  • Publication number: 20110204019
    Abstract: Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
    Type: Application
    Filed: November 15, 2010
    Publication date: August 25, 2011
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Jonathan Bornstein, David Hansen, Steven W. Longcor
  • Patent number: 8003511
    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: August 23, 2011
    Inventors: Darrell Rinerson, Jonathan Bornstein, Robin Cheung, David Hansen, Steven W. Longcor, Rene Meyer, Lawrence Schloss
  • Patent number: 7897951
    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 1, 2011
    Inventors: Darrell Rinerson, Jonathan Bornstein, Robin Cheung, David Hansen, Travis Byonghyop Oh
  • Patent number: 7888711
    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 15, 2011
    Inventors: Robin Cheung, Darrell Rinerson, Travis Byonghyop Oh, Jonathan Bornstein, David Hansen
  • Patent number: 7832090
    Abstract: Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 16, 2010
    Inventors: Jonathan Bornstein, David Hansen, Steven W. Longcor
  • Publication number: 20100159641
    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
    Type: Application
    Filed: December 18, 2009
    Publication date: June 24, 2010
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Jonathan Bornstein, David Hansen, Robin Cheung, Steven W. Longcor, Rene Meyer, Lawrence Schloss
  • Publication number: 20100155953
    Abstract: Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 24, 2010
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventor: Jonathan Bornstein
  • Publication number: 20100155723
    Abstract: Examples of memory stack cladding are described, including a memory stack, comprising a first electrode formed on a substrate, a conductive metal oxide layer deposited on the first electrode, a tunnel barrier layer comprising an insulating metal oxide, the tunnel barrier layer being deposited on the conductive metal oxide layer, a second electrode formed on the tunnel barrier layer, a glue layer deposited on the second electrode, a mask layer deposited on the glue layer, and a cladding layer deposited substantially over one or more surfaces of the memory stack, the cladding layer being configured to provide a barrier to prevent one or more hydrogen ions from diffusing through the one or more surfaces of the memory stack. The memory stack may define a two-terminal non-volatile memory cell operative to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 24, 2010
    Applicant: Unity Semiconductor Corporation
    Inventors: Jonathan Bornstein, Julie Casperson Brewer
  • Patent number: 7742323
    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: June 22, 2010
    Inventors: Darrell Rinerson, Jonathan Bornstein, Robin Cheung, David Hansen, Travis Byonghyop Oh