Abstract: A method and a device for distributing patterns to scanning engines for scanning packets in a packet stream are provided. The method includes providing a plurality of scanning engines and patterns, calculating a respective distance metric for every pair of patterns, and providing a plurality of distribution functions. Further, the method includes calculating a respective sum of the calculated distance metrics for distributing the patterns for each of the distribution functions, and utilizing the sums for selecting a distribution function of the D distribution functions for distributing the patterns to the M scanning engines. A device for implementing the method is also provided.

Abstract: A method and a device for distributing patterns to scanning engines for scanning packets in a packet stream are provided. The method includes providing a plurality of scanning engines and patterns, calculating a respective distance metric for every pair of patterns, and providing a plurality of distribution functions. Further, the method includes calculating a respective sum of the calculated distance metrics for distributing the patterns for each of the distribution functions, and utilizing the sums for selecting a distribution function of the D distribution functions for distributing the patterns to the M scanning engines. A device for implementing the method is also provided.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.