Patents by Inventor Jonathan C. Lueker

Jonathan C. Lueker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7719878
    Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Jonathan C. Lueker, Robert W. Faber
  • Publication number: 20090222601
    Abstract: A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.
    Type: Application
    Filed: September 18, 2008
    Publication date: September 3, 2009
    Inventors: Dean Warren, Jonathan C. Lueker
  • Patent number: 7286387
    Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 23, 2007
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Jonathan C. Lueker, Robert W. Faber
  • Patent number: 7222052
    Abstract: Briefly, one or more memory access parameters used to access a memory cell are adjusted based on a sensed operating temperature. In one embodiment, a pulse width of an access voltage is increased as the operating temperature decreases below a threshold. In another embodiment, a drive voltage is decreased as the operating temperature increases.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Jonathan C. Lueker
  • Patent number: 7218545
    Abstract: Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Jonathan C. Lueker, Richard L Coulson
  • Patent number: 7003599
    Abstract: A pipelined Universal Serial Bus (USB) parallel frame delineator and non-return to zero invert (NRZI) decoder is described. Using a three-stage pipeline and parallel data stream processing, a USB transceiver delineates received asynchronous frame boundaries within a USB peripheral NRZI data stream. Using asynchronous parallel data stream processing the USB transceiver concurrently decodes received NRZI encoded data.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Dean Warren, Jonathan C. Lueker
  • Patent number: 6922350
    Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: July 26, 2005
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Jonathan C. Lueker, Robert W. Faber
  • Patent number: 6907096
    Abstract: In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to detect the transitions between two logic levels in said transmitted data which are stored in groups of m sets of said n edge results which are, in turn output at a clock frequency which is the second frequency divided by m, for further processing.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 14, 2005
    Assignee: Intel Corporation
    Inventors: Jonathan C. Lueker, Dean Warren, Kenneth B. Oliver
  • Patent number: 6883047
    Abstract: A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventors: Dean Warren, Jonathan C. Lueker
  • Publication number: 20040062070
    Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventors: Richard L. Coulson, Jonathan C. Lueker, Robert W. Faber
  • Patent number: 6647444
    Abstract: Incoming serial data which is received M bits at a time where M=N, N+1 or N−1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: November 11, 2003
    Assignee: Intel Corporation
    Inventors: Jonathan C. Lueker, Dean Warren
  • Publication number: 20030079071
    Abstract: A pipelined Universal Serial Bus (USB) parallel frame delineator and non-return to zero invert (NRZI) decoder is described. Using a three-stage pipeline and parallel data stream processing, a USB transceiver delineates received asynchronous frame boundaries within a USB peripheral NRZI data stream. Using asynchronous parallel data stream processing the USB transceiver concurrently decodes received NRZI encoded data.
    Type: Application
    Filed: October 24, 2001
    Publication date: April 24, 2003
    Applicant: Intel Corporation
    Inventors: Dean Warren, Jonathan C. Lueker
  • Publication number: 20030063018
    Abstract: A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.
    Type: Application
    Filed: May 25, 2001
    Publication date: April 3, 2003
    Applicant: Intel Corporation
    Inventors: Dean Warren, Jonathan C. Lueker
  • Publication number: 20020087755
    Abstract: Incoming serial data which is received M bits at a time where M=N, N+1 or N−1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Jonathan C. Lueker, Dean Warren
  • Patent number: 6130896
    Abstract: In one embodiment of the invention, an access point for use in a powerline based network includes first physical layer circuitry to interface with a powerline and second physical layer circuitry to interface with an antenna. The access point also includes circuitry to interface between the first and second physical layer circuitry. The first and second physical layer circuitry and the circuitry to interface between the first and second physical layer circuitry allow an untethered electrical device to have data communication through the powerline with an electrical device tethered to the powerline. Under another embodiment of the invention, a powerline based network includes a powerline and an access point connected to the powerline and capable of wireless communication.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: October 10, 2000
    Assignee: Intel Corporation
    Inventors: Jonathan C. Lueker, Scott B. Blum, Steven D. Kassel, Phil W. Martin
  • Patent number: 5333154
    Abstract: A digital data generation system including a programmable dominance RS flip-flop has a random access memory that stores a user selected sequence of test data. A pattern formatting logic circuit receives the test data and produces, for each data period, a coarsely timed candidate pulse for identifying the leading edge of an output data pulse and a coarsely timed candidate pulse for identifying the trailing edge of the output data pulse. A precision delay circuit finely tunes the timing of the candidate pulses. The finely tuned pulses are applied to an RS flip-flop circuit which can be programmed for set or reset dominance, thereby preventing an indeterminate state when a logic "1" is applied to both the set and the reset input. In the system, the flip-flop is programmed so that the most recent of the lead pulse or the trail pulse prevails.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: July 26, 1994
    Assignee: Tektronix, Inc.
    Inventors: John A. Hengeveld, Jonathan C. Lueker, Bradford H. Needham, Burt Price, James Schlegel, Mehrab Sedeh
  • Patent number: 4967175
    Abstract: An inductor and carrier suitable for mounting on a mounting substrate includes an etched sheet of a bonded copper layer and polyimide film to form a film carrier. The periphery of the film carrier is patterned with a plurality of windows and a plurality of conductors, each conductor having a bent-up tab and and end portion terminating at the periphery within the respective window. A microminiature inductor core having a plurality of insulated windings is soldered to the respective bent-up tab of each conductor and the end portion of each conductor is then welded to bonding pads on the mounting substrate.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: October 30, 1990
    Assignee: Tektronix, Inc.
    Inventors: William E. Berg, Jonathan C. Lueker
  • Patent number: 4504809
    Abstract: A miniature latching thermomagnetic relay is disclosed which offers high contact forces, small size, and low cost. Ferromagnetic material is placed upon heaters in a low thermal conductivity substrate. A permanent magnet beneath the substrate attracts a moving element above the substrate. Contact points on the substrate and the moving element from electrical connections.A control signal causes a heater to warm the ferromagnetic material, changing the saturation flux density of the material. This results in an unbalanced force on the moving element, causing it to rock about a pivot point to open or close connections as desired. Planar fabrication techniques may be used to construct the relay.
    Type: Grant
    Filed: May 15, 1984
    Date of Patent: March 12, 1985
    Inventors: Jonathan C. Lueker, Raymond A. Zandonatti
  • Patent number: 4403183
    Abstract: An active voltage probe receiving a DC power voltage via an outer conductor of a coaxial cable is disclosed. The probe includes a differential amplifier with inputs connected to input and reference terminals via DC paths and a follower amplifier with an input connected to the input terminal via an AC path. Outputs currents from the differential and follower amplifiers are applied to an inner conductor of the coaxial cable.
    Type: Grant
    Filed: April 10, 1981
    Date of Patent: September 6, 1983
    Assignee: Tektronix, Inc.
    Inventor: Jonathan C. Lueker