Patents by Inventor Jonathan Callan

Jonathan Callan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060242517
    Abstract: Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic 22; wherein said detection logic is operable to detect a data or instruction access to at least one predetermined address and in response to not detecting said data or instruction access within said predetermined time, said control logic is operable to send a control signal to said data processor, said control signal controlling said data processor to perform a predetermined operation.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 26, 2006
    Inventors: Christopher Pedley, Jonathan Callan, Hedley Francis
  • Publication number: 20060101247
    Abstract: A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a data processing operation on one or more data values. Shift logic is operable to selectively apply a shift operation to data to produce one of the data values for the data processing operation. Further, a plurality of registers are provided for storing data. The instruction has a register specifier field for identifying a register and a shift specifier field for specifying a shift to be applied to that register's data in order to produce one of the data values for the data processing operation.
    Type: Application
    Filed: October 26, 2004
    Publication date: May 11, 2006
    Applicant: ARM LIMITED
    Inventors: Jonathan Callan, David Mansell, Christopher Pedley, David Seal
  • Publication number: 20050160210
    Abstract: There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said excepti
    Type: Application
    Filed: November 17, 2003
    Publication date: July 21, 2005
    Applicant: ARM Limited
    Inventors: Simon Watt, Christopher Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Brochier, David Mansell, Jonathan Callan