Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.

Abstract: A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.

Abstract: A waste disposal docking system includes a first sleeve to secure to a septic tank hose connection fitting; an angled PVC fitting having a second end of the first sleeve attached; a septic tank hose extending from the septic tank hose connection fitting, through the first sleeve and through the angled PVC fitting; a housing with a motor attached thereto; an extension device engaged with the housing to extend and contract via the motor; a second sleeve attached to a second end of the angled PVC fitting; the extension device engages with an end of the septic tank hose to extend and contract the septic tank hose; the septic tank hose is extended and contracted inside the second sleeve, the second sleeve extending and contracting therewith; and an end of the septic tank hose is to engage with a sewer cleanout station.

Abstract: A waste disposal docking system includes a first sleeve to secure to a septic tank hose connection fitting; an angled PVC fitting having a second end of the first sleeve attached; a septic tank hose extending from the septic tank hose connection fitting, through the first sleeve and through the angled PVC fitting; a housing with a motor attached thereto; an extension device engaged with the housing to extend and contract via the motor; a second sleeve attached to a second end of the angled PVC fitting; the extension device engages with an end of the septic tank hose to extend and contract the septic tank hose; the septic tank hose is extended and contracted inside the second sleeve, the second sleeve extending and contracting therewith; and an end of the septic tank hose is to engage with a sewer cleanout station.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.

Abstract: An oscilloscope apparatus and method of processing waveform data using a streaming architecture. The apparatus has multiple processing objects (processors) that share a common cache memory in which the waveform data is stored during processing. Each processing object performs a sequential processing operation by retrieving a “chunk” or portion of the waveform from the memory, processes the chunk of data, and re-stores the processed data into the same location in the cache memory. This process is generally repeated until the entire waveform has been sequentially processed. The apparatus operates using a “pull” design wherein the last processor requests the next chunk to be processed from the preceding processor. In this manner, the waveform data is essentially processed by pulling it through the sequence of processing objects. The multiple processing objects may be implemented as a sequence of software processing objects in a processing thread or as separate hardware processors.

Abstract: A layout versus schematic (LVS) comparison tool performs layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell.

Abstract: A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins.

Abstract: An oscilloscope apparatus and method of processing waveform data using a streaming architecture. The apparatus has multiple processing objects (processors) that share a common cache memory in which the waveform data is stored during processing. Each processing object performs a sequential processing operation by retrieving a “chunk” or portion of the waveform from the memory, processes the chunk of data, and re-stores the processed data into the same location in the cache memory. This process is generally repeated until the entire waveform has been sequentially processed. The apparatus operates using a “pull” design wherein the last processor requests the next chunk to be processed from the preceding processor. In this manner, the waveform data is essentially processed by pulling it through the sequence of processing objects. The multiple processing objects may be implemented as a sequence of software processing objects in a processing thread or as separate hardware processors.

Abstract: A method and apparatus for configuring and performing processing in a digital oscilloscope. The method comprises the steps of receiving one or more instructions and defining a plurality of processing elements based upon the received instructions. The plurality of processing elements is connected to define a processing web for performing a desired processing. The plurality of processing elements is synchronized to generate a synchronized result.