Abstract: A high-speed phase-frequency detection module is described to function at very high frequencies and to produce very low jitter. In one embodiment, high-speed phase-frequency detection module includes a PFD with edge-triggered asynchronous-reset true-single-phase-clocking (“TSPC”) D flip-flops that have very short CLK to Q and Reset to Q time delays. In one embodiment, the high-speed phase-frequency detection module includes a charge pump, without replica or feedback, that can respond to the very narrow pulses from the PFD and produce output voltages with small ripple, thus leading to low VCO output jitter.

Abstract: Tuning of a filter circuit is accomplished by determining a real RC time constant value for the filter circuit, then comparing the real RC vale to a predetermined RC value. If the real RC value does not match the predetermined RC value, the real RC value is varied (e.g.