Patents by Inventor Jonathan Chu

Jonathan Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250300798
    Abstract: A network device may be communicatively coupled to a remote device by a full-duplex communication link. The network device may perform link flap damping based on local and remote fault information and may signal, via a remote fault indication, a link flap damping state to the remote device.
    Type: Application
    Filed: March 22, 2024
    Publication date: September 25, 2025
    Inventors: Jonathan Chu, Nathanael Dattappa
  • Patent number: 11431601
    Abstract: A method of monitoring power systems over a wireless network protocol. The method includes receiving input waveform data containing a power event, capturing a pair of windows of the waveform data proximate to the power event, determining a hash for each of the pairs of window of waveform data, comparing each determined hash of each of the pair of windows to a library of hashes of previously encountered events, and based on the comparison of each determined hash of each pair of windows, transmitting the raw waveform of at least one of the pair windows over the wireless network protocol to an event detection system.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 30, 2022
    Assignee: VERDIGRIS TECHNOLOGIES, INC.
    Inventor: Jonathan Chu
  • Publication number: 20210144077
    Abstract: A method of monitoring power systems over a wireless network protocol. The method includes receiving input waveform data containing a power event, capturing a pair of windows of the waveform data proximate to the power event, determining a hash for each of the pairs of window of waveform data, comparing each determined hash of each of the pair of windows to a library of hashes of previously encountered events, and based on the comparison of each determined hash of each pair of windows, transmitting the raw waveform of at least one of the pair windows over the wireless network protocol to an event detection system.
    Type: Application
    Filed: August 9, 2018
    Publication date: May 13, 2021
    Inventor: Jonathan CHU
  • Patent number: 10114427
    Abstract: An input/output module baffle is adapted to an electronic device. The electronic device includes a motherboard and a casing. The motherboard is located inside the casing and includes a connector module. The input/output module baffle includes a fixing plate, a conductive component and a frame. The fixing plate includes a plurality of retaining clips to clamp the fixing plate on the connector module. The conductive component is located between the fixing plate and the connector module. The frame is located between the fixing plate and the casing. Moreover, a motherboard with the input/output module baffle is also disclosed herein.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: October 30, 2018
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Yao-Hsun Huang, Yu-Chen Lee, Shu-Fen Huang, I-Cheng Yeh, Jonathan Chu, Ming-Hung Chung
  • Patent number: 9839329
    Abstract: Disclosed is a frying pan holder including a frame structure including a pair of vertical frames that are spaced apart from each other and are vertically formed, and one or more horizontal frames that connect the pair of vertical frames, and a plurality of holding members, each of which includes a pair of outer holding parts, each of which has a protrusion coupled to a corresponding one of the pair of vertical frames at one end thereof and has an opposite end that is horizontally curved, and an inner holding part formed between the pair of outer holding parts, wherein the plurality of holding members are formed on one side or opposite sides of the frame structure.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: December 12, 2017
    Assignee: NA SEUNG HITECH CO., LTD.
    Inventor: Jonathan Chu
  • Publication number: 20170332504
    Abstract: An input/output module baffle is adapted to an electronic device. The electronic device includes a motherboard and a casing. The motherboard is located inside the casing and includes a connector module. The input/output module baffle includes a fixing plate, a conductive component and a frame. The fixing plate includes a plurality of retaining clips to clamp the fixing plate on the connector module. The conductive component is located between the fixing plate and the connector module. The frame is located between the fixing plate and the casing. Moreover, a motherboard with the input/output module baffle is also disclosed herein.
    Type: Application
    Filed: April 6, 2017
    Publication date: November 16, 2017
    Inventors: Yao-Hsun HUANG, Yu-Chen LEE, Shu-Fen HUANG, I-Cheng YEH, Jonathan CHU, Ming-Hung CHUNG
  • Publication number: 20170224176
    Abstract: Disclosed is a frying fan holder including a frame structure including a pair of vertical frames that are spaced apart from each other and are vertically formed, and one or more horizontal frames that connect the pair of vertical frames, and a plurality of holding members, each of which includes a pair of outer holding parts, each of which has a protrusion coupled to a corresponding one of the pair of vertical frames at one end thereof and has an opposite end that is horizontally curved, and an inner holding part formed between the pair of outer holding parts, wherein the plurality of holding members are formed on one side or opposite sides of the frame structure.
    Type: Application
    Filed: July 22, 2016
    Publication date: August 10, 2017
    Inventor: Jonathan CHU
  • Publication number: 20060190900
    Abstract: A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least one level of the hierarchy to be employed with the at least some circuit components of the circuit layout, wherein the interconnect segments interconnect the plurality of pins. A route estimator is employed to estimate lengths of the interconnect segments based on the pin locations of the plurality of pins. The estimated interconnect segment lengths are then employed in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.
    Type: Application
    Filed: January 21, 2005
    Publication date: August 24, 2006
    Applicant: International Business Machines Corporation
    Inventors: Yiu-Hing Chan, Jonathan Chu
  • Publication number: 20060171420
    Abstract: Message Synchronization of the present inventions begins with storing messages (e-mail, voice mail, faxes) in more than one (1) message repository allowing users multiple, differentiated access points (e.g.: IP Client, PSTN). From any of these points, messages can be altered to reflect any one or more of a number of defined messages states (e.g.: Deleted, Read, Unread). As a seamless service to the user, these changed states are reflected identically throughout the face of all access points, and the bodies of all repositories.
    Type: Application
    Filed: December 9, 2005
    Publication date: August 3, 2006
    Inventors: Jonathan Chu, Franco Yuvienco
  • Patent number: 7082595
    Abstract: A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition of cell physical position in the horizontal direction, a definition of the cell's vertical stacking level, a definition of the cell orientation, a specification of vertical alignment of multiple cell instances, and a definition of vertical spacing between 2 adjacent cell instances. These input parameters are used to generate a layout with the placed circuit elements.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: July 25, 2006
    Assignee: International Business Machines Corporation
    Inventors: Yiu-Hing Chan, Jonathan Chu, George D. Gristede, Gregory A. Northrop
  • Patent number: 6999469
    Abstract: Message Synchronization of the present inventions begins with storing messages (e-mail, voice mail, faxes) in more than one (1) message repository allowing users multiple, differentiated access points (e.g.: IP Client, PSTN). From any of these points, messages can be altered to reflect any one or more of a number of defined messages states (e.g.: Deleted, Read, Unread). As a seamless service to the user, these changed states are reflected identically throughout the face of all access points, and the bodies of all repositories.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: February 14, 2006
    Assignee: CyberTel, Inc.
    Inventors: Jonathan Chu, Franco Yuvienco
  • Patent number: D821166
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: June 26, 2018
    Assignee: NA SEUNG HITECH CO., LTD.
    Inventor: Jonathan Chu
  • Patent number: D832665
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: November 6, 2018
    Assignee: NA SEUNG HITECH CO., LTD.
    Inventor: Jonathan Chu