Patents by Inventor Jonathan Cromwell

Jonathan Cromwell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6484283
    Abstract: The present invention is a method and apparatus for encoding and decoding a turbo code. In the encoder, an interleaver interleaves and delays a block of input bits to generate interleaved input bits and delayed input bits. A first encoder generates a first, second, and third encoded bits. A second encoder generates a fourth encoded bit. A symbol generator generates a plurality of symbols which correspond to the input bits. In a decoder, a sync search engine detects a synchronizing pattern and extracts symbols from the encoded bits. An input buffer is coupled to the sync search engine to store the extracted symbols. A first soft-in-soft-out (SISO1) is coupled to the input buffer to generate a first soft decision set based on the extracted symbols. An interleaver is coupled to the SISO1 to interleave the first soft decision set. A second soft-in-soft-out (SISO2) is coupled to the input buffer and the interleaver to generate a second soft decision set.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: November 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Karen J. Stephen, Hon W. Lam, Jonathan Cromwell
  • Publication number: 20020029362
    Abstract: The present invention is a method and apparatus for encoding and decoding a turbo code. In the encoder, an interleaver interleaves and delays a block of input bits to generate interleaved input bits and delayed input bits. A first encoder generates a first, second, and third encoded bits. A second encoder generates a fourth encoded bit. A symbol generator generates a plurality of symbols which correspond to the input bits. In a decoder, a sync search engine detects a synchronizing pattern and extracts symbols from the encoded bits. An input buffer is coupled to the sync search engine to store the extracted symbols. A first soft-in-soft-out (SISO1) is coupled to the input buffer to generate a first soft decision set based on the extracted symbols. An interleaver is coupled to the SISO1 to interleave the first soft decision set. A second soft-in-soft-out (SISO2) is coupled to the input buffer and the interleaver to generate a second soft decision set.
    Type: Application
    Filed: December 30, 1998
    Publication date: March 7, 2002
    Inventors: KAREN J. STEPHEN, HON W. LAM, JONATHAN CROMWELL
  • Patent number: 6014682
    Abstract: Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate are disclosed. The Variable Rate Down-Sampling Filter allows a continuous range of sample rates to be derived from input samples at a fixed rate. The output rate does not have to be related to the fixed input rate in any integral or rational way, and in fact, the output rate can vary in time such as will occur when tracking a signal received from a station using a different timebase. A fixed sampling rate at the A/D Converter greatly simplifies the design of the analog front end. A single anti-aliasing filter can be designed and precisely matched to the fixed sampling rate. Used with a frequency-modulated numerically controlled oscillator (NCO), the Down-Sampling Filter keeps the entire frequency-synthesis and time-tracking loop in the digital domain. The need for an analog time-tracking loop to adjust the sampling instant at the A/D converter is eliminated.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: January 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Karen J. Stephen, Alok Gupta, Jonathan Cromwell