Abstract: A method for determining the position of an underwater device includes placement of a plurality of station keeping devices on or below the surface of the water in known positions. A device to locate is provided for placement below the surface of the water, and the device to locate and the station keeping devices are provided with a synchronized time base and a common acoustic pulse time schedule. Each station keeping device sends an acoustic pulse at a time according to the common acoustic pulse schedule. The device to locate receives pulses sent by the station keeping devices and calculates a distance between itself and each station keeping device based upon the time that the acoustic pulse is sent and the time that the pulse is received. The device to locate then calculates its position based upon the distances between the device to locate and the station keeping devices. Systems and devices are also disclosed.

Abstract: A power controller combines a multitude of smart battery packs into a single large bank, providing balanced charging and discharging. Battery packs are connected in parallel to form groups that may then be connected in series, while the specification limits for current and voltage of individual packs are maintained through microprocessor control of the battery pack charging circuits. The state of each pack is monitored, and charging of a pack at too high a charge is inhibited until the other packs in the group are sufficiently charged to allow balanced current-sharing. The state of each battery is broadcast on a bus to all processors so that each may determine whether there are enough packs of similar charge to safely source a load. The system preferably incorporates management firmware that allows user monitoring of the status of the power subsystem and all connected battery packs.

Abstract: An apparatus is provided for reducing read latency for an I/O device residing on a bus having a short read latency timeout period. The apparatus includes a I/O bridge on an I/O bus having a longer read latency timeout which modifies read transactions into two separate transactions, a write transaction to the same address requested by the read transaction which will force a write-back if the address hits in the CPU's write-back cache, and then performing the read transaction which is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the I/O bus having a short read latency timeout period from exceeding it's read latency timeout limit.

Abstract: An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.