Patents by Inventor Jonathan Curtis

Jonathan Curtis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190303143
    Abstract: A method and apparatus are provided for dynamically determining when an operation, specified by one or more instructions in a data processing system, is suitable for accelerated execution. Data indicators are maintained, for data registers of the system, that indicate when data-flow from a register derives from a restricted source. In addition, instruction predicates are provided for instructions to indicate which instructions are capable of accelerated execution. From the data indicators and the instruction predicates, the microarchitecture of the data processing system determines, dynamically, when the operation is a thread-restricted function and suitable for accelerated execution in a hardware accelerator. The thread-restricted function may be executed on a hardware processor, such as a vector, neuromorphic or other processor.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Arm Limited
    Inventors: Jonathan Curtis Beard, Curtis Glenn Dunham, Alejandro Rico Carro
  • Patent number: 10423446
    Abstract: Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configur
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Curtis Glenn Dunham, Jonathan Curtis Beard, Roxana Rusitoru
  • Patent number: 10423510
    Abstract: An apparatus comprises a plurality of memory units organized as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Prakash S. Ramrakhyani, Jonathan Curtis Beard
  • Patent number: 10353826
    Abstract: A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 16, 2019
    Assignee: Arm Limited
    Inventors: Jonathan Curtis Beard, Roxana Rusitoru, Curtis Glenn Dunham
  • Patent number: 10353601
    Abstract: A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 16, 2019
    Assignee: Arm Limited
    Inventor: Jonathan Curtis Beard
  • Publication number: 20190102272
    Abstract: An apparatus comprises a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 4, 2019
    Inventors: Prakash S. RAMRAKHYANI, Jonathan Curtis BEARD
  • Publication number: 20190018785
    Abstract: A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.
    Type: Application
    Filed: November 21, 2017
    Publication date: January 17, 2019
    Applicant: Arm Limited
    Inventors: Jonathan Curtis BEARD, Roxana RUSITORU, Curtis Glenn DUNHAM
  • Publication number: 20190018787
    Abstract: A host machine uses a range-based address translation system rather than a conventional page-based system. This enables address translation to be performed with improved efficiency, particularly when nest virtual machines are used. A data processing system utilizes range-based address translation to provide fast address translation for virtual machines that use virtual address space.
    Type: Application
    Filed: November 21, 2017
    Publication date: January 17, 2019
    Applicant: Arm Limited
    Inventors: Roxana Rusitoru, Jonathan Curtis Beard, Curtis Glenn Dunham
  • Publication number: 20190018794
    Abstract: A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Applicant: ARM LTD
    Inventors: Jonathan Curtis BEARD, Roxana RUSITORU, Curtis Glenn DUNHAM
  • Publication number: 20190018786
    Abstract: A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.
    Type: Application
    Filed: November 21, 2017
    Publication date: January 17, 2019
    Applicant: Arm Limited
    Inventors: Jonathan Curtis Beard, Stephan Diestelhorst
  • Publication number: 20190018790
    Abstract: A system, apparatus and method are provided in which a range of virtual memory addresses and a copy of that range are mapped to the same first system address range in a data processing system until an address in the virtual memory address range, or its copy, is written to. The common system address range includes a number of divisions. Responsive to a write request to an address in a division of the common address range, a second system address range is generated. The second system address range is mapped to the same physical addresses as the first system address range, except that the division containing the address to be written to and its corresponding division in the second system address range are mapped to different physical addresses. First layer mapping data may be stored in a range table buffer and updated when the second system address range is generated.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Applicant: ARM LTD
    Inventors: Jonathan Curtis BEARD, Roxana RUSITORU, Curtis Glenn DUNHAM
  • Publication number: 20190018808
    Abstract: A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Applicant: ARM LTD
    Inventors: Jonathan Curtis BEARD, Roxana RUSITORU, Curtis Glenn DUNHAM
  • Publication number: 20190018789
    Abstract: Memory address translation apparatus comprises a translation data store to store one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space; detector circuitry to detect whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data store; in which the detector circuitry is configured, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, to retrieve one or more further instances of the translation data; and translation circuitry to apply the
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Applicant: ARM LTD
    Inventors: Jonathan Curtis BEARD, Roxana RUSITORU, Curtis Glenn DUNHAM
  • Publication number: 20180293169
    Abstract: A virtual link buffer provides communication between processing threads or cores. A first cache is accessible by a first processing device and a second cache accessible by a second processing device. An interconnect structure couples between the first and second caches and includes a link controller. A producer cache line in the first cache stores data produced by the first processing device and the link controller transfers data in the producer cache line to a consumer cache line in the second cache. Each new data element is stored at a location in the producer cache line indicated by a store position or tail indicator that is stored at a predetermined location in the same cache line. Transferred data are loaded from a location in the consumer cache line indicated by a load position or head indicator that is stored at a predetermined location in the same consumer cache line.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: ARM Ltd
    Inventors: Jonathan Curtis BEARD, Peter VAN HENSBERGEN
  • Patent number: 10067708
    Abstract: Data synchronization between memories of a data processing system is achieved by transferring the data blocks from a first memory to a second memory, forming a hash list from addresses of data blocks that are written to the second memory or modified in the second memory. The hash list may be to identify a set of data blocks that are possibly written to or modified. Data blocks that are possibly modified may be written back from the second memory to the first memory in response to a synchronization event. The hash list may be updated by computing, in hardware or software, hash functions of an address of the transferred or modified data block to determine bit positions to be set. The hash list may be queried by computing hash functions of an address to determine bit positions, and checking bits in the hash list at those bit positions.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 4, 2018
    Assignee: Arm Limited
    Inventor: Jonathan Curtis Beard
  • Publication number: 20180150322
    Abstract: Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configur
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Curtis Glenn DUNHAM, Jonathan Curtis BEARD, Roxana RUSITORU
  • Publication number: 20180150315
    Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Curtis Glenn DUNHAM, Jonathan Curtis BEARD, Roxana RUSITORU
  • Publication number: 20180150243
    Abstract: A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Applicant: ARM Limited
    Inventor: Jonathan Curtis BEARD
  • Publication number: 20180150321
    Abstract: Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Curtis Glenn DUNHAM, Jonathan Curtis BEARD, Roxana RUSITORU
  • Publication number: 20180023095
    Abstract: A device and a method to sense changes in the environment and log the sensed changes.
    Type: Application
    Filed: July 25, 2016
    Publication date: January 25, 2018
    Inventors: Jonathan Curtis Beard, Gary Dale Carpenter