Patents by Inventor Jonathan D. Coker

Jonathan D. Coker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10127933
    Abstract: A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 13, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sharat Batra, Jonathan D. Coker, Travis R. Oenning
  • Publication number: 20170365280
    Abstract: A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.
    Type: Application
    Filed: August 11, 2017
    Publication date: December 21, 2017
    Inventors: SHARAT BATRA, JONATHAN D. COKER, TRAVIS R. OENNING
  • Patent number: 9741369
    Abstract: A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: August 22, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sharat Batra, Jonathan D. Coker, Travis R. Oenning
  • Patent number: 9236066
    Abstract: In general, techniques are described for writing data to a storage device that comprises an interface and a controller. The interface may receive a request to sequentially write data stored in a first group of tracks to an I-region, where the first group of tracks was also previously written. The controller may move data stored in a second group of consecutive tracks different than the first group of tracks from the I-region to an E-region, the second group having cardinality equal to the tracks that must be moved for the first group to be written sequentially in the I-region. The E-region comprises a portion of the storage device reserved for temporary storage. The controller may determine a position of the I-region where data from one of the second group was previously stored, and write data from the first group of tracks sequentially to the I-region, starting at the position.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: January 12, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Jonathan D. Coker, David R. Hall, Shad H. Thorstenson
  • Patent number: 9230578
    Abstract: The present invention generally relates to a read head in a magnetic recording head. The read head utilizes two reader elements that are stacked in the down track direction within the same read gap to improve resolution and SNR by combining the signals from the two reader elements. The output waveform from each read element is asymmetric in the down track direction; however, by use of equalizer settings and waveform combining the algorithm in signal processing, the combined waveform has a similar or better resolution and higher SNR compared to a single read element in a smaller read gap.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: January 5, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Sharat Batra, Jonathan D. Coker, Travis R. Oenning
  • Publication number: 20150248900
    Abstract: A system according to one embodiment includes a magnetic head having a plurality of sensors arranged to simultaneously read at least three immediately adjacent data tracks on a magnetic medium, wherein none of the sensors share more than one lead with any other of the sensors. Such embodiment may be implemented in a magnetic data storage system such as a disk drive system, which may include a magnetic head, a drive mechanism for passing a magnetic medium (e.g., hard disk) over the magnetic head, and a controller electrically coupled to the magnetic head.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Sharat Batra, Jonathan D. Coker, Travis R. Oenning
  • Publication number: 20150179193
    Abstract: The present invention generally relates to a read head in a magnetic recording head. The read head utilizes two reader elements that are stacked in the down track direction within the same read gap to improve resolution and SNR by combining the signals from the two reader elements. The output waveform from each read element is asymmetric in the down track direction; however, by use of equalizer settings and waveform combining the algorithm in signal processing, the combined waveform has a similar or better resolution and higher SNR compared to a single read element in a smaller read gap.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: Sharat BATRA, Jonathan D. COKER, Travis R. OENNING
  • Patent number: 9001450
    Abstract: A method of correcting repeatable run out (RRO) errors for a HDD in which RRO data is instead stored in consolidated form within the reserved area of the disk, instead of storing RRO data in the servo patterns for each HDD track or sector. RRO data is preferably stored in the reserved area of a hard disk drive in compressed form. The compressed RRO data is subsequently read into DRAM in compressed form and then decompressed for use. Predictive techniques determine what compressed RRO data is needed for upcoming read/write operations.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 7, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Jonathan D. Coker, Jeffrey L. Furlong, David R. Hall, David J. Stanek
  • Publication number: 20130342929
    Abstract: A method of correcting repeatable run out (RRO) errors for a HDD in which RRO data is instead stored in consolidated form within the reserved area of the disk, instead of storing RRO data in the servo patterns for each HDD track or sector. RRO data is preferably stored in the reserved area of a hard disk drive in compressed form. The compressed RRO data is subsequently read into DRAM in compressed form and then decompressed for use. Predictive techniques determine what compressed RRO data is needed for upcoming read/write operations.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Applicant: HGST NETHERLANDS B.V.
    Inventors: Jonathan D. Coker, Jeffrey L. Furlong, David R. Hall, David J. Stanek
  • Patent number: 7482965
    Abstract: A chirp waveform generator for producing a chirp waveform ƒ(t)=sin (t2 modulus m) where modulus m is represented by n submoduli and/or factored submoduli m1-mn. Sequence generators generate digital sequence values representative of sequences of quadratic residues for each submoduli and/or factored submoduli m1-mn. Sine and cosine digital-to-analog converters (DACs) connected to the sequence generators receive the digital sequence values for each submoduli and/or factored submoduli m1-mn and produce sequences of corresponding analog sine and cosine signals. An analog processor including adders and multipliers connected to the DACs combines the sine and cosine signals to produce the chirp waveform. The argument (t2 modulus m) is an implemented phase argument that approximates a desired phase argument (?rt2). Programmable inputs on the sequence generators enable control over waveform parameters including starting phase, ramp rate and frequency.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 27, 2009
    Assignee: Mayo Foundation for Medical Education and Research
    Inventors: Jonathan D. Coker, Robert A. Kertis
  • Publication number: 20080262320
    Abstract: A system for monitoring a physical parameter of a subject includes a sensor, a transmitter, a repeater, and a base station. The sensor is located within the body of the subject and is operable to sense a physical parameter of the subject. The transmitter is electrically connected to the sensor, and is operable to transmit a spread spectrum encoded signal using a digital spreading code, the encoded signal carrying information indicative of the sensed physical parameter and being transmitted to a local region outside the body. The repeater is located in the local region, is movable with the subject, and is operable to receive the transmitted encoded signal and retransmit it to a remote region outside the body. The base station is located in the remote region and is operable to receive and decode the retransmitted encoded signal.
    Type: Application
    Filed: June 28, 2006
    Publication date: October 23, 2008
    Inventors: Timothy M. Schaefer, Daivd R. Holmes, Jonathan D. Coker, Edward B. Welch, Barry K. Gilbert, Kenton R. Kaufman
  • Patent number: 6643814
    Abstract: Maximum transition run encoding of a succession of M-bit data words to produce a succession of N-bit code words, where N→−M, for supply to a magnetic recording channel is described. Each M-bit data word is encoded in accordance with an MTR coding scheme to produce a G-bit word, where N→−G→M, such that the maximum number of consecutive bits of a first value, generally bits of value “1”, in a succession of the G-bit words is limited to a first predetermined value j1. The G-bit word is then encoded to produce an N-bit word in accordance with a second coding scheme.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: November 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Jonathan D. Coker, Evangelos S. Eleftheriou, Richard L. Galbraith, Dave James Stanek
  • Patent number: 6625235
    Abstract: In a maximum likelihood sequence detector for symbol sequences which were equalized in a PR4 equalizer, noise prediction means (35) are provided including infinite impulse response (IIR) filtering, which have noise-whitening capabilities and are imbedded into the maximum likelihood detection process. The resulting INPML detector (10) can be implemented in digital or analog circuit technology. In addition, a DC-notch filter (44a) and a stochastic gradient procedure can be provided for DC offset compensation and for MR head or signal asymmetry compensation.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Richard L. Galbraith, Evangelos S. Eleftheriou, Walter Hirt
  • Patent number: 6557124
    Abstract: A method and apparatus for encoding a plurality of successive m-bit binary data words to produce a plurality of successive of n-bit binary code words, where n and m are positive integers and n is greater than m, for supply to a magnetic recording channel. Each m-bit binary data word is partitioned into a plurality of blocks of bits, and at least one said blocks of bits in each m-bit binary data word is encoded in accordance with a finite-state coding scheme to produce a plurality of successive n-bit binary code words. At least one stage of violation correction which transforms the plurality of successive n-bit binary code words. Violation correction includes detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations within each n-bit binary coded word, and replacing any prohibited bit pattern so detected by a corresponding substitute bit pattern.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Jonathan D. Coker, Evangelos S. Eleftheriou, Richard L. Galbraith, Todd C. Truax
  • Patent number: 6222879
    Abstract: A method and apparatus for automating the convergence of tap weights in an equalizer for a data channel is disclosed. The automated equalization method is contained within the channel and obtains a temporary copy of each of a plurality of current tap weights from a current tap weight memory, determines a direction for modifying the temporary copy of each of the plurality of current tap weights, constrains the modifications to the temporary copy of each of the plurality of current tap weights to produce adjusted tap weights and at the end of a read operation, stores the adjusted tap weights to the current tap weight memory for use during a next read operation.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Jonathan D. Coker, Evangelos S. Eleftheriou, Richard L. Galbraith, John J. Stephenson
  • Patent number: 6158027
    Abstract: A noise-predictive data detection method and apparatus are provided for enhanced noise-predictive maximum-likelihood (NPML) data detection in a direct access storage device. A data signal from a data channel in the direct access storage device is applied to a maximum-likelihood detector that provides an estimated sequence signal. A noise bleacher filter having a frequency response of (1+.alpha.D)/1-.beta.D.sup.2) receives a combined estimated sequence signal and data signal and provides a noise filtered signal. A matching and error event filter receives the noise filtered signal and provides an error event filtered signal. An error correction unit receives the estimated sequence signal from the maximum-likelihood detector and receives the error event filtered signal and provides an error corrected estimated sequence signal.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: December 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Gregory S. Bush, Roy D. Cideciyan, Jonathan D. Coker, Evangelos S. Eleftheriou, Richard L. Galbraith, David J. Stanek
  • Patent number: 5619539
    Abstract: A method and apparatus are provided for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: April 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Francois B. Dolivo, Richard L. Galbraith, Reto J. Hermann, Walter Hirt, Kevin Vannorsdel
  • Patent number: 5438460
    Abstract: Apparatus and method for asynchronous gain adjustment are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) having a normal operating range and a filter, gain and timing control coupled to the ADC. A plurality of samples are detected from the ADC. Each of the detected samples are sequentially compared with predetermined threshold values. The predetermined threshold values include a zero value, and a minimum value and a maximum value of the normal operating range of the ADC. An absolute value of each of the detected samples are sequentially compared with a forth predetermined threshold value. A gain adjustment correction value is determined utilizing the sequentially compared values.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: August 1, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Richard L. Galbraith
  • Patent number: 5426541
    Abstract: Apparatus and method for providing equalization adjustment for a filter are provided in a PRML data channel. A first predetermined test pattern is written. Relative error is measured in both magnitude and phase for predetermined frequencies. A relative magnitude ratio for the predetermined frequencies and a phase delay between the predetermined frequencies are identified. A tap set is generated having predefined frequency responses at a plurality of predefined discrete frequencies.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: June 20, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Richard L. Galbraith, Walter Hirt, David J. Stanek, Mark D. Warne
  • Patent number: 5416806
    Abstract: Timing loop apparatus and method are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) providing samples to a digital filter during a tracking mode and to a gain and timing control during an acquisition mode. Sample values from the ADC are received at peaks and zeros on sync field pattern. An error absolute value is calculated from the received ADC sample values and an error sign of the calculated error absolute valve calculated using a most significant bit of the current and a previous sample. Timing correction values are calculated responsive to the calculated error absolute value and applied to a clock gated register that latches and holds the generated timing correction values for a predefined number of clock cycles.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: May 16, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Coker, Richard L. Galbraith