Patents by Inventor Jonathan D. Harms
Jonathan D. Harms has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954499Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.Type: GrantFiled: August 10, 2022Date of Patent: April 9, 2024Assignee: Micron Technology, Inc.Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
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Patent number: 11914449Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).Type: GrantFiled: May 9, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventor: Jonathan D. Harms
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Patent number: 11861493Abstract: Data may be abstracted and/or masked prior to being provided to a machine learning model for training. A machine learning model may provide a confidence level associated with a result. If the confidence level is too high, the machine learning model or an application including the machine learning model may refrain from providing the result as an output. In some examples, the machine learning model may provide a “second best” result that has an acceptable confidence level. In other examples, an error signal may be provided as the output. In accordance with examples of the present disclosure, data may be abstracted and/or masked prior to being provided to a machine learning model for training and confidence levels of results of the trained machine learning model may be used to determine when a result should be withheld.Type: GrantFiled: April 21, 2020Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Dmitry Vengertsev, Zahra Hosseinimakarem, Jonathan D. Harms
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Publication number: 20230410873Abstract: Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bit error rate) as a function of refresh rate based on statistical data for decay of capacitance within the cells of the device with time. In one variant, error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth, since refresh operations have been reduced or eliminated. In another variant, an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device, In yet another embodiment, error-intolerant applications operate the memory with a reduced or eliminated refresh, and cells or regions of the memory not adequately refreshed by presumed random read/write operations of the memory over time are actively refreshed.Type: ApplicationFiled: August 25, 2023Publication date: December 21, 2023Inventors: David Hulton, Jeremy Chritz, Jonathan D. Harms
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Patent number: 11847183Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).Type: GrantFiled: February 18, 2022Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventor: Jonathan D. Harms
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Publication number: 20230253064Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.Type: ApplicationFiled: March 31, 2023Publication date: August 10, 2023Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
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Publication number: 20230187010Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.Type: ApplicationFiled: December 20, 2022Publication date: June 15, 2023Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman
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Patent number: 11631473Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.Type: GrantFiled: August 11, 2021Date of Patent: April 18, 2023Assignee: Micron Technology, Inc.Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
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Patent number: 11585654Abstract: Embodiments of the disclosure are drawn to projecting light on a surface and analyzing the scattered light to obtain spatial information of the surface and generate a three dimensional model of the surface. The three dimensional model may then be analyzed to calculate one or more surface characteristics, such as roughness. The surface characteristics may then be analyzed to provide a result, such as a diagnosis or a product recommendation. In some examples, a mobile device is used to analyze the surface.Type: GrantFiled: June 2, 2020Date of Patent: February 21, 2023Assignee: MICRON TECHNOLOGY, INC.Inventors: Zahra Hosseinimakarem, Jonathan D. Harms, Alyssa N. Scarbrough, Dmitry Vengertsev, Yi Hu
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Publication number: 20230033704Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.Type: ApplicationFiled: August 10, 2022Publication date: February 2, 2023Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
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Patent number: 11557371Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.Type: GrantFiled: April 27, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman
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Patent number: 11520240Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.Type: GrantFiled: May 7, 2021Date of Patent: December 6, 2022Assignee: Micron Technology, Inc.Inventors: Nikolay A. Mirin, Robert Dembi, Richard T. Housley, Xiaosong Zhang, Jonathan D. Harms, Stephen J. Kramer
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Publication number: 20220351770Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Jonathan D. Harms, David Hulton, Jeremy Chritz
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Patent number: 11430539Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.Type: GrantFiled: June 29, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Troy A. Manning, Troy D. Larsen, Jonathan D. Harms, Glen E. Hush, Timothy P. Finkbeiner
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Publication number: 20220269332Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).Type: ApplicationFiled: May 9, 2022Publication date: August 25, 2022Inventor: Jonathan D. Harms
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Patent number: 11422826Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.Type: GrantFiled: May 19, 2020Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
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Publication number: 20220261062Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Inventor: Jonathan D. Harms
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Patent number: 11398264Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.Type: GrantFiled: December 14, 2020Date of Patent: July 26, 2022Assignee: Micron Technology, Inc.Inventors: Jonathan D. Harms, David Hulton, Jeremy Chritz
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Publication number: 20220199155Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.Type: ApplicationFiled: December 27, 2021Publication date: June 23, 2022Inventors: Jonathan J. Strand, Sukneet Singh Basuta, Shashank Bangalore Lakshman, Jonathan D. Harms
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Publication number: 20220171826Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventor: Jonathan D. Harms