Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

Abstract: Disclosed embodiments relate to systems and methods for performing matrix row-wise and column-wise permute instructions. In one example, a processor includes fetch circuitry to fetch an instruction, decoding, using decode circuitry, the fetched instruction having fields to specify an opcode and locations of a source matrix and a destination matrix, the opcode indicating the processor is to perform a permutation by copying, into each of a plurality of equal-sized logical partitions of the destination matrix, a selected logical partition of a same size from the source matrix, the selection being indicated by a permute control, and execution circuitry to execute the decoded instruction as per the opcode.

Abstract: Disclosed embodiments relate to systems and methods for performing nibble-sized operations on matrix elements. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction the fetched instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode to indicate the processor is to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix. The exemplary processor includes execution circuitry to execute the decoded instruction as per the opcode.

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

Abstract: Methods and systems are disclosed for folded antenna structures that allow for receive and/or transmit antennas to be used for portable or other devices. The folded antennas described herein can be configured, for example, to fit the design constraints and considerations for portable devices. The folded antenna structures can be implemented using relatively flat flexible printed circuits (e.g., flex circuits) and can be placed in available spaces within the portable device, such as above or behind a battery, while still providing good performance characteristics. Still further, the folded antenna structures can be implemented on a printed circuit board and/or as part of plastic materials and pieces included as part of a portable device.

Abstract: Systems and methods are disclosed for the co-location of radio frequency (RF) antennas in portable devices, portable devices and their docking stations and related systems, and devices with restrictive space constraints to allow for simultaneous receive (RX) and transmit (TX) operation without degradation. The systems and methods disclosed overcome RX channel degradation, receiver performance, and other problems seen in prior solutions. More particularly, transmit and receive antennas are oriented to provide for cross-polarization of their electro-magnetic fields, are oriented to allow one or both antenna to fall within null regions of the other antenna, and/or oriented with both cross-polarization and null region considerations in mind. Other variations and implementations are also described.

Abstract: Methods and systems are disclosed for folded antenna structures that allow for receive and/or transmit antennas to be used for portable or other devices. The folded antennas described herein can be configured, for example, to fit the design constraints and considerations for portable devices. The folded antenna structures can be implemented using relatively flat flexible printed circuits (e.g., flex circuits) and can be placed in available spaces within the portable device, such as above or behind a battery, while still providing good performance characteristics. Still further, the folded antenna structures can be implemented on a printed circuit board and/or as part of plastic materials and pieces included as part of a portable device.

Abstract: Systems and methods are disclosed for the co-location of radio frequency (RF) antennas in portable devices, portable devices and their docking stations and related systems, and devices with restrictive space constraints to allow for simultaneous receive (RX) and transmit (TX) operation without degradation. The systems and methods disclosed overcome RX channel degradation, receiver performance, and other problems seen in prior solutions. More particularly, transmit and receive antennas are oriented to provide for cross-polarization of their electro-magnetic fields, are oriented to allow one or both antenna to fall within null regions of the other antenna, and/or oriented with both cross-polarization and null region considerations in mind. Other variations and implementations are also described.