Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.

Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.